Koninklijke Philips Corporation N.v.

Robertus Dominicus Joseph Verhaar

Guido Jozef Maria Dormans

Thomas James Davies

Guoqiao Tao

Antonius Maria Petrus Johannes Hendriks

Joachim Christoph Hans Garbe

Johannes Dijkstra

Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit () and a second option technology electronic circuit () as functional parts of a system-on-chip, by:

Multilevel poly-Si tiling for semiconductor circuit manufacture

The invention relates to a semiconductor device having a byte-erasable EEPROM memory comprising a matrix of rows and columns of memory cells. In order to provide a semiconductor device having a byte-erasable EEPROM which has a reduced chip size and increased density and which is suitable for low-power applications it is proposed according to the present invention that the memory cells each comprise a selection transistor having a selection gate and, arranged in series therewith, a memory transistor having a floating gate and a control gate, the selection transistor being further connected to a source line of the byte-erasable EEPROM memory, which source line is common for a plurality of memory cells, and the memory transistor being further connected to a bit line of the byte-erasable EEPROM memory, wherein the columns of memory cells are located in separate p-type wells separated by n-type wells. Preferably, high voltage switching elements are provided for dividing global control gates into local control gates for each column of bytes.

Semiconductor device having a byte-erasable EEPROM memory

A semiconductor device comprising a non-volatile memory cell ( ) for storing a bit, arranged in a semiconductor substrate ( ) containing a first dopant type, the memory cell including a drain ( ) in the substrate ( ), a floating gate ( ), a control gate ( ), a thin gate isolation layer ( ), and an insulating layer ( ), the insulating layer ( ) being above the floating gate ( ), the control gate ( ) being above the insulating layer ( ), the floating gate ( ) being above the thin gate isolation layer ( ), and the cell further including an access transistor ( ) for controlling access to the non-volatile memory cell ( ), the cell ( ) including a buried substrate layer ( ) containing a second dopant type and a source ( ), and the access transistor ( ) being formed in the substrate ( ), in a trench adjacent to the floating gate ( ), said trench extending substantially from the source ( ) to the substrate's surface.

Two-transistor flash cell

Virtual-ground, split-gate flash memory cell arrangements and method for producing same

Semiconductor device

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Nijmegen, Netherlands

Robertus Dominicus Joseph Verhaar