U.S. Philips Corporation

Robertus D Verhaar

Leendert De Bruin

Guido J Dormans

Herbert Lifka

Roger Cuppens

Paulus A Van Der Plas

Josephus M Van Laarhoven

Andrew J Walker

Johannes A Van Ooijen

The invention provides a method of combining an EPROM (or EEPROM) with a standard CMOS process. After growing the gate oxide 9, a lightly doped polycrystalline or amorphous silicon layer 10, hereinafter referred to as poly I, is deposited. In this layer, the floating gate 13 of the memory cells is defined, while, outside the memory matrix, the surface remains covered with poly I. Subsequently, the source/drain implantation in the memory cells is carried out. The poly layer 10 situated outside the memory matrix is masked against this heavy implantation by the mask 11. Subsequently, a second poly layer can be provided from which the control gates of the memory cells are formed and which forms a coherent layer with the existing poly I layer outside the matrix. In a subsequent series of steps in a standard CMOS process, the n-ch MOSTs and p-ch MOSTs are provided, n-type gates 22 for the n-ch MOSTs and p-type gates 23 for the p-ch MOSTs being formed from the poly I layer.

Method of manufacturing a non-volatile memory and a CMOS transistor

The invention relates in particular, though not exclusively, to an integrated circuit with an embedded non-volatile memory with floating gate (10). According to the invention, at least two poly layers of equal or at least substantially equal thickness are used for this device. The first poly layer, poly A, is for the floating gate (10) and for the gates (22) of NMOS and PMOS in the logic portion of the circuit. The second poly layer, poly B, serves exclusively for the control electrode (21) above the floating gate. If so desired, a third poly layer may be deposited for both the control electrode and the logic gates, so that the thicknesses of these electrodes, and thus their resistances, are given desired values. Problems like overetching and bridging during saliciding are prevented in that the control electrode and the logic gates have the same thickness.

Semiconductor device having an embedded non-volatile memory and method

Very thin tunnel oxides are used in conventional non-volatile memories to obtain a sufficiently strong tunnelling current to or from the floating gate. Usual thicknesses of the tunnel oxide lie in the 8-10 nm range. The invention renders it possible to use tunnel oxides of a much greater thickness, for example of the order of 20 nm, for comparable tunnelling current values. According to the invention, the tunnelling effect is enhanced by implantation of a heavy, high-energy ion, for example As, into a comparatively thin poly layer of the oxide. During this, Si atoms are propelled from the polylayer into the oxide, so that the oxide is enriched with Si, which causes a major change in the tunnelling characteristics. The same oxide which functions as a gate oxide elsewhere may be used for the tunnel oxide. An important advantage of the invention is that direct contact between the tunnel oxide and photoresist layers necessary during the process is avoided, so that the properties of the tunnel oxide are not or at least substantially not impaired by the photoresist.

Method of manufacturing a semiconductor device having a non-volatile

Electrical connection is provided to a device region (3,4) bounded by an insulating region (12a,12b,9) and adjacent one major surface (1a) of a semiconductor body (1) by applying a flowable organic material to form an organic layer (20) on the one major surface (1a), defining a masking layer (30) over the organic layer (20), etching the organic layer (20) selectively with respect to the underlying device and insulating regions through a window (31) in the masking layer (30) to form an opening (21) exposing a contact area (11) of the device region (3,4) and depositing electrically conductive material, for example tungsten, to form a conductive pillar (40) within the opening (21) in contact with the contact area (11). The organic layer (20) is then removed so as to expose the conductive pillar (40), a layer 50 of insulating material is provided over the pillar, the insulating layer is etched to expose a top surface of the pillar and electrically conductive material deposited to contact the pillar (40).

Method of producing conductive pillars in semiconductor device

A method of manufacturing mask alignment marks on an active surface of a semiconductor substrate (12) is disclosed, in which first, at least one layer (13) of a material resistant to oxidation is formed on the active surface, after which by a local etching of this layer, zones (15') for isolation by a field oxide, are defined simultaneously with the alignment marks (17'). There are formed, after the local etching of the layer (13) of anti-oxidation material while using the remaining parts of the anti-oxidation layer as a mask, depressions (26) at the substrate surface of a given depth at least at locations containing the alignment marks, which locations are designated as alignment windows (18) and the surface of the substrate is then exposed within the windows, and finally a thermal oxidation step is effected to obtain the field oxide (19'), during which the alignment marks (18) are simultaneously covered by oxide (24).

Method of providing mask alignment marks

Electrical connection to a device region (3,4) of a semiconductor device is formed by providing a semiconductor body (1) having adjacent one major surface (12) a device region (3,4) bounded by an insulating region (19a,19b,9), providing an activating layer (11) on the one major surface (12), applying a flowable material as a layer (13) of photosensitive resist, exposing and developing the resist to define an opening (14) over a contact area (12a) of the device region (3,4), and selectively plating electrically conductive material into the opening (14) to form a conductive pillar (15) in electrical contact with the contatct area (12a). The layer (13) of photosensitive resist is removed after formation of the conductive pillar (15) and a layer of insulating material is then provided to cover the conductive pillar (15) and the surface (12). The insulating layer is then etched to expose a top surface (15a) of the conductive pillar (15).

Selectively plating conductive pillars in manufacturing a semiconductor

A method is set forth comprising the deposition of a first and a second polycrystalline conducting layer, which are separated by an insulating layer, with the object of creating gate islands which extend in the direction of highly doped parts (22b, 23b) of source and drain zones. According to the invention, the gate islands (15) the first delimited in the first polycrystalline layer (12), after which the edges of these islands are protected with provisional spacers (20a) of an oxidation-preventing material, so that after ion implantation of the weakly doped portions (22, 23) of the source and drain, non-protected parts of the device can be re-oxidized. After this, the provisional spacers (20a) are removed and the second polycrystalline layer (30) is deposited, thus achieving electrical contact with the previously protected edges of the islands (15) of the first polycrystalline layer (12). Widened gate islands are finally formed by the insulating spacer technique (32).

Method of manufacturing a device comprising MIS transistors having a

Method is set forth of manufacturing a device comprising MIS transistors having a projecting gate on the weakly doped parts of source and drain regions. A method comprising the deposition of a first and a second polycrystalline conducting layer, which are separated by an insulating layer. According to the invention, gate islands (20) are formed in the second polycrystalline layer (14) and the ion implantation of the weakly doped portions (21, 22) of the source and drain zones is effected through the assembly of the insulating layer (13) and the first polycrystalline layer (12). A third polycrystalline layer (23) is then deposited, which layer contacts both the island of the second polycrystalline layer (14) and the first polycrystalline layer (12). Widened gate islands (26) are finally marked off by means of the insulating spacer technique (25), in which islands there remain only present the portions (23') of the third polycrystalline layer (23) in the shape of an 'L'. The highly doped portions (28, 29) of the source and drain zones are then implanted.

A magnetic sensor (1) includes a magneto-resistive element (3) which magnetically bridges a gap (15) between two magnetic flux conductors (6,7). In order to reduce the noise level and higher harmonic distortion of the sensor, each of the flux conductors (6,7) includes at least two layers (16,18) of magnetically permeable materials having substantially the same composition between which a layer (17) is present which has a different composition.

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Eindhoven, Netherlands

Robertus D Verhaar