Stmicroelectronics S.r.l.

Roberto Zafalon

Danilo Pietro Pau

Andrea Mario Veggetti

Cristina Silvano

Vittorio Zaccaria

Carlo Guardiani

Nicola Dragone

Roberta Burger Riccio

Mariagiovanna Sami

Donatella Sciuto

An architecture for a pipeline processor circuit, preferably of the VLIW type, comprises a plurality of stages and a network of forwarding paths which connect pairs of said stages, as well as a register file for operand write-back. An optimization-of-power-consumption function is provided via inhibition of writing and subsequent readings in said register file of operands retrievable from said forwarding network on account of their reduced liveness length.

Processor architecture

A method of reducing power consumption of an electric circuit having a primary supply voltage and first and second circuit blocks is discussed. The method includes determining for the first circuit block an operation time for a first critical path of the first circuit block and determining for the second circuit block an operation time of a second critical path of the second circuit block. From those operation times, the method determines that the operation time of the first critical path is faster than the operation time of the second critical path. The method then creates a first supply voltage for the first circuit block that is less than the primary supply voltage in response to determining that the operation time of the first critical path is faster than the operation time of the second critical path.

Performance driven multi-valued variable supply voltage scheme for low power design of VLSI circuits and systems

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Venice, Italy

Roberto Zafalon