Micron Technology Incorporated

Stmicroelectronics S.r.l.

Roberto Somaschini

Fabio Pellizzer

Samuele Sciarrillo

Marcello Ravasio

Paolo Tessariol

Giulio Albini

Alessandro Vaccaro

Cristina Casellato

Carmela Cupeta

Innocenzo Tortorelli

Antonino Rigano

Giorgio Allegato

Laura Oggioni

Matteo Garavaglia

Ombretta Donghi

Riccardo Mottadelli

Michele Magistretti

Gabriel L Donadio

Nicola Nastasi

Pietro Petruzza

The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.

Cross-point memory and methods for fabrication of same

Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

Forming array contacts in semiconductor memories

Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.

Self-aligned interconnection for integrated circuits

A microelectromechanical device having a first substrate of semiconductor material and a second substrate of semiconductor material having a bonding recess delimited by projecting portions, monolithic therewith. The bonding recess forms a closed cavity with the first substrate. A bonding structure is arranged within the closed cavity and is bonded to the first and second substrates. A microelectromechanical structure is formed in a substrate chosen between the first and second substrates. The device is manufactured by forming the bonding recess in a first wafer; depositing a bonding mass in the bonding recess, the bonding mass having a greater depth than the bonding recess; and bonding the two wafers.

MEMS device formed by at least two bonded structural layers and manufacturing process thereof

A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.

A roughened silicon surface is formed by a process including repetitively performed roughening cycles. Each roughening cycles including a step for depositing a non-planar polymeric layer over an area of a silicon body and a step for plasma etching the polymeric layer and the area of the silicon body etch in a non-unidirectional way. As a result, a surface portion of the silicon body is removed, in a non-uniform way, to a depth not greater than 10 nm.

Process for manufacturing a microelectronic device having a black surface, and microelectronic device

The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can also include an electrically inactive stack structure located at an edge of the stack structure.

Memory cell array structures and methods of forming the same

Growing community of inventors

Vimercate, Italy

Roberto Somaschini