Stmicroelectronics S.r.l.

Roberto Modica

Antonello Santangelo

Salvatore Cascino

Viviana Cerantonio

Maurizio Moschetti

Salvatore Leonardi

Alessandro Auditore

Piero Fallica

Giuseppe Arena

A sensor of volatile substances includes: a first electrode structure and a second electrode structure capacitively coupled, comb-fingered, and arranged coplanar in a plane; and a sensitive layer, of a sensitive material that is permeable to a volatile substance and has electrical permittivity depending upon a concentration of the volatile substance absorbed by the sensitive material. The sensitive layer extends from opposite sides of the plane.

Sensor of volatile substances and process for manufacturing a sensor of volatile substances

A sensor of volatile substances including: a sensitive layer, of a sensitive material that is permeable to a volatile substance and has an electrical permittivity depending upon a concentration of the volatile substance absorbed; a first electrode structure and a second electrode structure capacitively coupled together and arranged so that a capacitance between the first electrode structure and the second electrode structure is affected by the electrical permittivity of the sensitive material; and a supply device, configured to supply a heating current through one between the first electrode structure and the second electrode structure in a first operating condition, so as to heat the sensitive layer.

Sensor of volatile substances with integrated heater and process for manufacturing a sensor of volatile substances

A process for manufacturing an electronic semiconductor device, wherein a SOI wafer is provided, formed by a bottom layer of semiconductor material, an insulating layer, and a top layer of semiconductor material, stacked on top of one another; alignment marks are formed in the top layer; an implanted buried region is formed, aligned to the alignment marks; a hard mask is formed on top of the top layer so as to align it to the alignment marks; using the hard mask, the top layer is selectively removed so as to form a trench extending up to the insulating layer; there a lateral-insulation region in the trench, that is contiguous to the insulating layer and delimits with the latter an insulated well of semiconductor material; and electronic components are formed in the top layer.

Process for the aligned manufacture of electronic semiconductor devices in a SOI substrate

A bipolar device is integrated in an active layer, wherein delimitation trenches surround respective active areas housing bipolar transistors of complementary types. Each active area accommodates a buried layer; a well region extending on top of the buried layer; a top sinker region extending between the surface of the device and the well region; a buried collector region extending on top of the well region and laterally with respect to the top sinker region; a base region, extending on top of the buried collector region laterally with respect to the top sinker region; and an emitter region extending inside the base region. The homologous regions of the complementary transistors have a similar doping level, being obtained by ion-implantation of epitaxial layers wherein the concentration of dopant added during the growth is very low, possibly zero.

Vertical-type, integrated bipolar device and manufacturing process thereof

A dielectric insulation structure is formed in a silicon layer by integrating a dielectric trench structure therein. The dielectric trench structure defines an insulation well where semiconductor devices are to be integrated therein. The dielectric trench structure is on a hollow region that is completely surrounded by a dielectric area. The dielectric area also forms the side insulation of the dielectric trench structure. The dielectric trench structure is interrupted by a plurality of points to define a plurality of side support regions for the insulation well.

Dielectric insulation structure for integrating electronic semiconductor devices and relevant manufacturing process

A vertical capacitor structure fabricated in a semiconductor substrate region overlaid by a buried oxide layer and a buried doped layer, as well as by a semiconductor layer that includes a sinker doped region in contact with the buried doped layer, wherein an oxide trench structure is formed, this oxide trench structure being filled with suitably doped polysilicon to produce, in combination with the sinker region, the plates of the vertical capacitor structure, with the oxide trench structure forming the dielectric therebetween. A process for integrating a vertical capacitor structure starting from a structure blank that includes a semiconductor substrate, a buried oxide layer and a buried doped layer is also provided.

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Mascalucia, Italy

Roberto Modica