Stmicroelectronics S.r.l.

Roberto Giorgio Bardelli

Stefano Passi

Giuseppe Maiocchi

Michele Berto Boscolo

Giovanni Cremonesi

Juri Giovannone

Mario Tarantola

Luca Milani

Andrea Gambero

Fausto Carace

Donata Rosaria Maria Nicolosi

Giovanni Lanfranchi

Silvio Fornera

Anna Moroni

Alessio Corso

The present invention relates to a system and a method for generating a plurality of control signals for multi-die applications. In particular, the invention relates to the generation of synchronized control signals generated by independent dies having an own local clock and provided with a common clock. In a first step, in each die, the period of the common clock signal is measured using a TDC. In further steps, in each die, a respective phase shift is evaluated and applied between the rising edge of the common clock signal and each of the rising edges of the output control signals, using delay unit.

System and method for generating a plurality of control signals in multi-die systems

A waveform generator includes a system control unit and signal channels controlled by the system control unit and configured to supply driving signals for driving a respective transducer of an array of transducers. Each signal channel includes a sequential access memory having rows, where each row contains an instruction word configured to generate a respective step of a waveform to be generated. A memory output of the sequential access memory is defined by an output row at a fixed location. The waveform to be generated is defined by a block of instruction words. Each signal channel also includes an internal control unit that is configured to sequentially move the content of the sequential access memory, based on the instruction word currently at the memory output, so that sequences of instruction words are provided at the output row.

Waveform generator

A memory includes a sequence of memory locations storing a corresponding sequence of state codes that specifying the shape of a waveform. The sequence of state codes is read from the memory and decoded by a long and toggle decoder circuit. The decoding operation generates a sequence of signal codes. When the state code is a long code, the sequence of signal codes includes same signal codes corresponding to a signal level of the waveform. When the state code is a toggle code, the sequence of signal codes includes a first signal code corresponding to one signal level of the waveform and a second signal code corresponding to another signal level of the waveform. A signal decode circuit then decodes the signal codes in the sequence of signal codes to generate the waveform for output which includes the signal levels corresponding to the decoded signal codes.

Waveform generator using a waveform coding scheme for both long states and toggle states

A digital representation of a waveform is generated based on signals received during a recording period. The received signals include a digital clock signal providing a determined number of clock pulses during the recording period, a plurality of binary digital signals defining, for each clock pulse of the determined number of clock pulses, a waveform state associated with the clock pulse. A digital representation of the waveform is generated and stored. The waveform has a duration based on the recording period and a profile based on the defined waveform states associated with the clock pulses of the determined number of clock pulses.

Method of setting a waveform signal in an ultrasound imaging apparatus and apparatus for setting an ultrasonic waveform signal using such method

An antifuse cell includes an antifuse capacitor that is activatable with a breakdown voltage to provide an electrically conductive path through the capacitor. A pull-up transistor is coupled to the antifuse capacitor. A current path of the pull-up transistor is arranged in parallel with the antifuse capacitor. A shooting transistor is coupled to the pull-up transistor with the current paths of the pull-up transistor and a current path of the shooting transistor cascaded to each other.

Antifuse cell with capacitor and transistors

A digital representation of a waveform is generated based on signals received during a recording period. The received signals include a digital clock signal providing a determined number of clock pulses during the recording period, a plurality of binary digital signals defining, for each clock pulse of the determined number of clock pulses, a waveform state associated with the clock pulse. A digital representation of the waveform is generated and storing. The waveform has a duration based on the recording period and a profile based on the defined waveform states associated with the clock pulses of the determined number of clock pulses.

A ring oscillator has a plurality of elementary units connected in cascade and linked in order to make a chain with the respective output terminals connected to the input terminals of the successive elementary units of the chain, the elementary units being crossed by a cyclic signal during a time period of activation, each of said elementary units comprising an auxiliary recovery terminal for temporarily resetting each elementary unit during each loop of said cyclic signal, said auxiliary recovery terminal being connected to an output terminal of a successive elementary unit of the chain.

Oscillator, time-digital converter circuit and relating method of time-digital measure

A control system for a phase generator including a delay block including delay units, and first and second multiplexers configured to receive output signals of each of the delay units and to respectively supply first and second output signals. The control system may include a controller configured to drive the first multiplexer and the second multiplexer respectively with a first select signal and a second select signal, a detection module configured to detect a phase difference between the first output signal and the second output signal and to generate a corresponding digital phase shift signal, the detection module including a phase comparator, and a Time-Digital converter circuit coupled thereto and having logic elements configured to generate the digital phase shift signal, and a logic circuit connected to the detection module and configured to process the digital phase shift signal and to generate a signal indicative of a control executed.

Control system for a phase generator and corresponding control method

An integrated control and power driving system moves a read/write head carrying arm over the surface of a disk. The integrated control and power driving system is applicable to a spindle motor, a mass storage disk drive and a voice-coil motor, for example, and includes a first chip and a second chip. The first chip integrates the output power stages driving the motors, and has an interface for outputting feedback signals representing functioning conditions of the voice-coil motor and of the spindle motor, and for receiving digital control signals of the output power stages. The second chip integrates logic drive and control circuitries of the power stages and an interface for receiving the feedback signals output by the first chip, and for transmitting to the first chip the digital control signals.

Control system of motors for rotating a disk and for positioning heads of a mass storage disk device

A frequency multiplier circuit and a controlling method thereof, which measures a period of a waveform by counting cycles of a fixed frequency timing signal, and reproduces the period by adding a number of prefixed length subperiods of the fixed frequency to the cycle count, making it as equal as possible to the period, so to minimize the reproduction error.

Frequency multiplier circuit and method using above circuit for a period time division in subperiods, for a brushless motor

A successive-approximation analog-digital converter including a logic control circuit timed by means of an external clock signal clock. The logic control circuit includes a register containing a first digital signal formed of N bits, which is the product of a first analog-digital conversion. The logic control circuit is suitable for producing a second digital signal formed of N bits through a second analog-digital conversion in N clock cycles. This analog-digital converter converts the second digital signal sent by the logic circuit to a second analog signal. A comparator compares the first analog signal with the second analog signal which has been input to the analog-digital converter. The converter includes a device which enables the increase of the first analog signal in output from the digital-analog converter and in input to the comparator by a preset value (Voffs) when the bit of the first digital signal which corresponds in position to the bit of the second digital signal which must be decided in a clock cycle is zero.

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Fino Mornasco, Italy

Roberto Giorgio Bardelli