Micron Technology Incorporated

Sgs-Thomson Microelectronics S.r.l.

Ovonyx Inc.

Stmicroelectronics S.r.l.

Other

Sgs-Thomson Microelectronics Limited

Sgs-Thomson Microelectronics S.a.

Sgs Microelettronica Spa

Roberto Gastaldi

Ferdinando Bedeschi

Guido Torelli

Cristiano Calligaro

Claudio Resta

Giulio Casagrande

Ward D Parkinson

Fabio Pellizzer

Tyler A Lowrey

Alessandro Manstretta

Paolo Tessariol

Paolo Rolandi

Roberto Bez

Vincenzo Daniele

Nicola Telecco

Paolo Giuseppe Cappelletti

Augusto Benvenuti

Loris Vendrame

Rino Micheloni

Paolo Amato

Giovanni Campardo

Marco Pasotti

Federico Pio

Marco Dallabora

Anna Maria Conti

Jean-Marie Bernard Gaultier

Piero Malcovati

Alessandro Grossi

David Novosel

Enzo M Donze

Alessandro Cabrini

Gerard S De Ferron

Bruno Beverina

Gianbattsista Lo Giudice

Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.

Apparatus and methods including a bipolar junction transistor coupled to a string of memory cells

A phase change memory device with memory cells () formed by a phase change memory element () and a selection switch (). A reference cell () formed by an own phase change memory element () and an own selection switch () is associated to a group () of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.

Phase change memory device

Methods and systems to refresh a nonvolatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.

Refresh architecture and algorithm for non-volatile memories

The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include programming a memory cell to an initial data state and determining a data state of the memory cell by applying a programming signal to the memory cell, the programming signal associated with programming memory cells to a particular data state, and determining whether the data state of the memory cell changes from the initial data state to the particular data state during application of the programming signal.

Resistance variable memory sensing

Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.

Read distribution management for phase change memory

Methods and systems to refresh a non-volatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.

A phase change memory device with memory cells is formed from a phase change memory element and a selection switch. A reference cell is formed from a similar phase change memory element and an associated selection switch and is associated to a group of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating for drift in the properties of the memory cells.

A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments.

Method for using a bit specific reference level to read a phase change memory

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Agrate Brianza, Italy

Roberto Gastaldi