Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Roberto Ganzelmi

Cesare Pozzi

Alberto Battaia

Saverio Pezzini

Raffaele Costa

Maurizio Peri

A method is for implementing at least one clock tree in a synchronous digital electronic circuit. The method may include selecting an interchangeable programmable delay buffer stage, calculating an expected skew based upon the selected interchangeable programmable delay buffer stage, and interchanging the selected interchangeable programmable delay buffer stage with another if the expected skew is different from a desired skew. A related synchronous digital electronic circuit includes a plurality of clock trees, and an interchangable programmable delay buffer stage connected to each of the clock trees.

Method of implementing clock trees in synchronous digital electronic circuits, and a programmable delay buffer stage therefor

The method relates to assembling modules for an integrated circuit comprising at least a plurality of modules. The method provides for the formation of at least one module architecture which comprises a plurality of modules and is aligned along one dimension of such modules. The invention also concerns an integrated circuit and a stacked module architecture obtained with the inventive assembling method.

Method of assembling modules to form a complex integrated circuit and corresponding module architecture

A complex integrated circuit comprises at least a plurality of modules coupled together through at least a system channel. The circuit further comprises a plurality of input/output devices for interfacing the circuit with structures outside the circuit. The plurality of input/output devices comprise at least a first circuit portion implemented as a module coupled to the remaining modules of the circuit by the first channel system (BUS1).

Input/output devices for complex integrated circuits, and assembly

A method whereby the N elements of a memory are read sequentially, and the data items contained therein are compared with reference data items. Simultaneously with the reading of each element of the memory, its address is written in a number of redundancy check registers, each connected to a respective redundancy element. In the event the element of the memory differs from the reference data item, the first of the redundancy check registers is blocked to prevent it from being overwritten and the address of a faulty element of the memory is permanently stored. Upon the entire memory being read, the addresses of any faulty elements in the memory are thus already stored in the redundancy check registers.

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Vittuone, Italy

Roberto Ganzelmi