Paul Scherrer Institut

Roberto Dinapoli

Bernd Schmitt

Aldo Mozzanica

Anna Bergamaschi

Xintian Shi

Beat Henrich

Roland Horisberger

Stefan Ritt

Gemma Tinti

A detector system which can be switched between single photon counting and charge integrating mode depending on the application, the photon flux and energy. Although the space for electronics in a pixel or strip detector system is very limited (as each channel is limited by the pixel size), the reconfiguration of the analog chain and the logic/counter in this smart way yields to have a detector system allowing both modes of operation and, therefore, effectively combining the characteristics of an Eiger® single photon counting system and a Jungfrau® charge integrating pixel detector system into one single detector. Depending on the application, the flux and the photon energy, the operator is enabled to switch between single photon counting and charge integrating mode of operation.

Dual mode detector

A system counts photon interactions in an array of photosensitive diodes and addresses the issue of improving position resolution. Every photo-detector diode of the array is connected to a readout unit cell containing a high-gain charge-to-voltage amplifier, a shaper, at least two comparators with independent thresholds and at least one interpixel communication logic, receiving as input signals from comparator outputs of the same readout unit cell and of the neighboring readout unit cells. This logic is then connected to at least one counter, each counter followed by a counter readout. By means of the digital interpixel communication logic and the set of comparators with different thresholds in every readout unit cell, it is possible to determine the photon hit position in the detector with a higher position resolution than the physical photo-detector size including the removal of the corner effect in pixel detectors.

Single photon counting detectors in strip or pixel design having digital inter-pixel communication logic comprising a physical area of each photo-detector diode being subdivided into a plurality of smaller sections representing a plurality of virtual channels

A single photon counting detector system has a layer of photosensitive material and an N&#xd7;M array of photo-detector diodes. Each photo-detector diode has a bias potential interface and a diode output interface. The bias potential interface is connected to bias potential. An N&#xd7;M array of high gain, low noise readout unit cells is provided, one readout unit cell for each photo-detector diode. Each readout unit cell has an input interface connected to the diode output interface, a high-gain voltage amplifier with an integration capacitor at least two parallel lines of digital counters, each having a comparator with an individually selectable threshold and a gateable section to determine the counting intervals of the digital counters. A multiplexer allows access to the readout cell unit either on a per pixel basis or for several pixels in parallel to read out the digital counter to a data processor transferring the data off chip.

Single photon counting detector system having improved counter architecture

A single photon counting pixel detector chip has a negligible dead time and consequentially high frame rates. The detector chip contains: a) a layer of photosensitive material; b) an N&#xd7;M array of photo-detector diodes arranged in the layer of photosensitive material; and c) a N&#xd7;M array of readout unit cells. The readout unit cell contains an input interface connected to a diode output interface, a high-gain charge to voltage amplifying device and a pixel counter being connected to an output of the high-gain voltage amplifying device. The pixel counter is split into a first number of nibble counters. The basic counter cell contains a counting element, a switch, a temporary storage element and an output stage. Additionally, the detector chip has a side shift register to read out the nibble counters row-wise with a predetermined number of nibble row selections.

Single photon counting readout chip with negligible dead time

A method relates to a technique for reducing the readout time of switched capacitor array circuitries. An implementation is a SCA chip capable of sampling 12 differential input channels at a sampling speed of 10 MSPS to 5 GSPS. The analog waveform can be stored in 1024 sampling cells per channel, and can be read out after sampling via a shift register. The write signal for the sampling cells is generated by a chain of inverters. The domino wave runs continuously until stopped. A read shift register clocks the contents of the sampling cells to outputs, where it can be digitized. It is possible to read out only a part of the waveform for reducing the digitization time. The high channel density, high analog bandwidth of 450 MHz, and low noise of 0.35 mV makes this chip suited for low power, high speed, high precision waveform digitizing.

Growing community of inventors

Brugg, Switzerland

Roberto Dinapoli