Stmicroelectronics S.r.l.

Micron Technology Incorporated

Ovonyx Inc.

Other

Sgs-thomson Microelectronics S.r.l.

Western Digital (fremont), Inc.

Roberto Bez

Fabio Pellizzer

Giulio Casagrande

Ferdinando Bedeschi

Roberto Gastaldi

Alessandro Grossi

Romina Zonca

Marina Tosi

Giorgio Servalli

Emilio Camerlenghi

Alberto Modelli

Agostino Pirovano

Lorenzo Fratin

Kyusik Sin

Matthew R Gibbons

Guido De Sandre

Hugh Craig Hiner

Caterina Riva

William D Jensen

Stefano Ratti

Damon E Van Gerpen

Tyler A Lowrey

Innocenzo Tortorelli

Marco Pasotti

Corrado Villa

Paolo Tessariol

Stephen J Hudgens

Marcello Mariani

Guy Charles Wicker

Paolo Giuseppe Cappelletti

Wolodymyr Czubatyj

Xizeng Shi

Marco Dallabora

Enrico Varesi

Hua-Ching Tong

Augusto Benvenuti

Paola Zuliani

Pietro Petruzza

Maria Santina Marangon

Daniele Cantarelli

Edward J Spall

Xizeng (Stone) Shi

David Esseni

Roberta Piva

Laura Aina

Fabio Pellizer

Paolo Cappeletti

Luca Selmi

A phase change memory device with memory cells () formed by a phase change memory element () and a selection switch (). A reference cell () formed by an own phase change memory element () and an own selection switch () is associated to a group () of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.

Phase change memory device

A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

Phase change memory cell and manufacturing method thereof using minitrenches

A phase change memory cell has first and second electrodes having phase change material there-between. The phase change memory cell is devoid of heater material as part of either of the first and second electrodes and being devoid of heater material between either of the first and second electrodes and the phase change material. A method of forming a memory cell having first and second electrodes having phase change material there-between includes lining elevationally inner sidewalls of an opening with conductive material to comprise the first electrode of the memory cell. Elevationally outer sidewalls of the opening are lined with dielectric material. Phase change material is formed in the opening laterally inward of and electrically coupled to the conductive material in the opening. Conductive second electrode material is formed that is electrically coupled to the phase change material. Other implementations are disclosed.

Phase change memory cells

Phase change memory cells and methods of forming phase change memory cells

A phase change memory device with memory cells is formed from a phase change memory element and a selection switch. A reference cell is formed from a similar phase change memory element and an associated selection switch and is associated to a group of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating for drift in the properties of the memory cells.

Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction.

Memory arrays and methods of forming memory cells

A fuse device has a fuse element provided with a first terminal and a second terminal and an electrically breakable region, which is arranged between the first terminal and the second terminal and is configured to undergo breaking as a result of the supply of a programming electrical quantity, thus electrically separating the first terminal from the second terminal. The electrically breakable region is of a phase-change material, in particular a chalcogenic material, for example GST.

Electrical fuse device based on a phase-change memory element and corresponding programming method

A method of making a non-volatile MOS semiconductor memory device includes a formation step, in a semiconductor material substrate, of STI isolation regions (shallow trench isolation) filled by field oxide and of memory cells separated each other by said STI isolation regions. The memory cells include a gate electrode electrically isolated from said semiconductor material substrate by a first dielectric layer, and the gate electrode includes a floating gate self-aligned to the STI isolation regions. The method includes a formation phase of said floating gate exhibiting a substantially saddle shape including a concavity; the formation step of said floating gate includes a deposition step of a first conformal conductor material layer.

Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling

A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.

Self-aligned bipolar junction transistors

A process for self-aligned manufacturing of integrated electronic devices includes: forming, in a semiconductor wafer having a substrate, insulation structures that delimit active areas and project from the substrate; forming a first conductive layer, which coats the insulation structures and the active areas; and partially removing the first conductive layer. In addition, recesses are formed in the insulation structures before forming said first conductive layer.

Process for self-aligned manufacture of integrated electronic devices

A process for manufacturing a phase change memory array includes the steps of: forming a plurality of phase change memory cells in an array region of a semiconductor wafer, the phase change memory cells arranged in rows and columns according to a row direction and to a column direction, respectively; forming a control circuit in a control region of the semiconductor wafer; forming a plurality of first bit line portions for mutually connecting phase change memory cells arranged on a same column; forming first level electrical interconnection structures; and forming second level electrical interconnection structures above the first level electrical interconnection structures. The first level electrical interconnection structures include second bit line portions laying on and in contact with the first bit line portions and projecting from the first bit line portions in the column direction for connecting the first bit line portions to the control circuit.

Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array thereby manufactured

Growing community of inventors

Milan, Italy

Roberto Bez