Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Alma Mater Studiorum-universitá Di Bologna

Roberto Antonio Canegallo

Pier Luigi Rolandi

Marco Pasotti

Alan H Kramer

Mauro Chinosi

Giovanni Gozzini

Roberto Guerrieri

Giovanni Guaitini

Marco Sabatini

Mauro Scandiuzzo

Ernestina Chioffi

Marco Tartagni

Luca Ciccarelli

Eleonora Franchi Scarselli

Danilo Gerna

Luca Magagni

Alberto Fazzi

Antonio Gnudi

Pierluigi Rolandi

Loris Giuseppe Navoni

Salvatore Valerio Cani

Claudio Mucci

Aldo Romani

Davide Dozza

Mauro Zanuccoli

Luca Perilli

Marco Crescentini

Luca Perugini

Giulio Ricotti

Nicolò Manaresi

Marco Marchesi

Domenico Cristaudo

Roberto Cardu

Andrea Lodi

Valentina Nardone

Frank Lhermet

Massimiliano Innocenti

Maximilian Sergio

Alessia Maria Elgani

Philip Leong

Michele Biondi

Alberto Pagani

Marcella Carissimi

Michele Borgatti

Eleonora Franchi

Federico Natali

Fabio Campi

Marco Onorato

Mario Toma

Roberto Giansante

Andrea Cappelli

Stefano Pucillo

Mauro Mirandola

Francesco Renzini

David Dozza

Cedric Issartel

Matteo D'Addato

Guerrieri Roberto

Mario Mirandola

A circuit includes a clock input node, a first signal input node configured to receive a first modulated signal switching between a first DC voltage and a second DC voltage, a bias circuit, a first output node, a first capacitor, a second capacitor, and switching circuitry coupled to the first capacitor and the second capacitor. Control circuitry is configured to initially set the switching circuitry in a first configuration in response to the first modulated signal having the second DC voltage, thereby charging the first capacitor to the second DC voltage and charging the second capacitor to the first DC voltage, and subsequently set the switching circuitry in a second configuration in response to an edge detected in the clock signal, thereby producing the first threshold voltage at the first output node after charge redistribution taking place between the first and second capacitors.

Threshold voltage generator circuit and corresponding receiver device

An embodiment memory device comprises a plurality of memory cells, each exhibiting a transconductance depending on a value of a stored bit, a plurality of bit lines associated with respective groups of memory cells, each bit line configured to flow a respective electric current indicative of the bit stored in a selected memory cell of the respective group of memory cells, and a computing circuit providing an output electric quantity indicative of a linear combination of a plurality of input electric quantities. The computing circuit comprises a biasing stage configured to bias each bit line with a respective input electric quantity, the electric current flowing through each bit line based on a product of the respective input electric quantity and the transconductance of the selected memory cell, and a combining stage for combining the electric currents flowing through the plurality of bit lines thereby obtaining the output electric quantity.

Memory device and method for in-memory computing

A planar Hall sensing element includes a first pair of sensing electrodes mutually opposed in a first direction across the sensing element and a second pair of sensing electrodes mutually opposed in a second direction across the sensing element, with the second direction orthogonal to the first direction. A first pair of bias electrodes is mutually opposed in a third direction and a second pair mutually opposed in a fourth direction across the sensing element, the fourth direction orthogonal to the third direction. The third and fourth directions are rotated 45&#xb0; with respect to the first and second directions so each sensing electrode is arranged between a bias electrode of the first pair and second pair. A DC bias current is supplied between the first and second pairs of bias electrodes. First and second Hall voltages are sensed at the first and second pairs of sensing electrodes.

Hall sensor, corresponding devices and method

In one example, a circuit includes a first node to receive an analog signal that is an amplitude modulated radio-frequency signal for a digital signal. An output node is configured to provide an output signal indicative of rising and falling edges of an envelope of the analog signal. The rising and falling edges are indicative of rising and falling edges of the digital signal. A first current path is disposed between a power supply node and the first node. The first current path includes a first transistor coupled between the first node and a first bias source. The first bias source is coupled between the first transistor and the power supply node. The output node is coupled to a first intermediate node in the first current path between the transistor and the first bias source. A control terminal of the first transistor is coupled to the output node via a feedback network.

Detection circuit, corresponding device and method

A Hall sensor may include a Hall sensing element configured to produce a Hall voltage indicative of a magnetic field when traversed by an electric current, and a first pair of bias electrodes mutually opposed in a first direction across the Hall sensing element. The Hall sensor may include a second pair of bias electrodes mutually opposed in a second direction across the Hall sensing element. The Hall sensor may include a first pair of sensing electrodes mutually opposed in a third direction across the Hall sensing element, and a second pair of sensing electrodes mutually opposed in a fourth direction across the Hall sensing element. The fourth direction may be orthogonal to the third direction, each sensing electrode being between a bias electrode of the first pair and a bias electrode of the second pair.

Hall sensor and sensing method, and corresponding device

A communication cell for an integrated circuit includes a physical interface configured to supply an input signal (for example, a capacitive signal or an ohmic signal). A receiver circuit operates to receive the capacitive signal and generate a first intermediate signal. A buffer circuit operates to receive the ohmic signal and generate a second intermediate signal. An output stage including a selector device (for example, a multiplexer) configured to receive the first and second intermediate signals and selectively pass only one of those signals to the integrated circuit based on operating condition. The input signal may further be an inductive signal, with the output stage further functioning to selectively pass that signal based on operating condition.

Communication cell for an integrated circuit operating in contact and contactless mode, electronic chip comprising the communication cell, electronic system including the chip, and test apparatus

An asynchronous level shifter electronic circuit including: a transmitter, which can be coupled to a first voltage and generates a communication signal; a receiver, which can be coupled to a second voltage; and a capacitive coupling stage, which receives the communication signal and supplies a corresponding filtered signal to the receiver. The receiver includes: a threshold device, which has an input terminal and an output terminal and switches an electrical quantity on the output terminal between a first value and a second value, as a function of corresponding transitions through a threshold of a first intermediate signal present on the input terminal, to generate a second intermediate signal; and a biasing circuit, which generates the first intermediate signal to have a d.c. component, which is a function of the second intermediate signal, and superposed on which is a variable component, which is a function of the filtered signal.

Capacitive coupling, asynchronous electronic level shifter circuit

A testing apparatus includes a tester and a probe card system that includes a probe card connected to the tester, and an active interposer connected to the probe card and wirelessly coupled with a device to be tested. The active interposer includes pads positioned on its free surface facing the device. The pads are positioned with respect to pads of the device so that each pad of the active interposer faces a pad of the device and is separated therefrom by a dielectric. Each pair of facing pads forms an elementary wireless coupling element which allows a wireless transmission between the active interposer and the device. The active interposer also includes an amplifier circuit configured to amplify wireless signals from the device before forwarding them to the tester. The probe card system includes a transmission element able to transmit a power voltage from the tester to the device.

Active probe card for electrical wafer sort of integrated circuits

A method includes communicatively coupling first and second integrated electronic devices together through a plurality of reference capacitors, transmitting a plurality of transmission reference signals on transmission reference electrodes of the plurality of reference capacitors, receiving coupling signals on reception reference electrodes of the plurality of reference capacitors, amplifying said coupling signals, generating a plurality of reception reference signals, generating a plurality of reception control signals as a function of the plurality of reception reference signals, and detecting a possible misalignment between said first and second integrated electronic devices based on the plurality of reception control signals.

Method for verifying the alignment between integrated electronic devices

An assembly including: a first substrate having a first surface and housing a first electrical-interconnection element and a second electrical-interconnection element in a position corresponding to the first surface; a second substrate having a second surface, housing a third electrical-interconnection element and a fourth electrical-interconnection element in a position corresponding to the second surface, and provided with a dielectric layer extending on top of the third interconnection element; and a first bump and a second bump made of conductive material, extending between the first electrical-interconnection element and the third electrical-interconnection element and, respectively, between the second electrical-interconnection element and the fourth electrical-interconnection element, at least partially aligned to the respective electrical-interconnection elements, the first bump being ohmically coupled to the first interconnection element and capacitively coupled to the third interconnection element, and the second bump being ohmically coupled to the second interconnection element and to the fourth interconnection element.

Substrate assembly provided with capacitive interconnections, and manufacturing method thereof

Contactless differential coupling structures can be used to communicate signals between circuits located on separate chips or from one chip to a probing device. The contactless coupling structures avoid problems (breaks, erosion, corrosion) that can degrade the performance of ohmic-type contact pads. The contactless coupling structures comprise pairs of conductive pads placed in close proximity. Differential signals are applied across a first pair of differential pads, and the signals are coupled wirelessly to a mating pair of conductive pads. Circuitry for generating and receiving differential signals is described.

Contact and contactless differential I/O pads for chip-to-chip communication and wireless probing

An embodiment of communication cell for enabling data communication between an integrated circuit and an electronic unit distinct from the integrated circuit, comprising a contact pad unit, configured for capacitively coupling, in a first operating condition of said communication cell, to the electronic unit for receiving an input signal from said electronic unit, and for ohmically coupling, in a second operating condition of said communication cell, to the electronic unit for receiving the input signal; a receiver device, including signal-amplifying means, coupled between said contact pad unit and said integrated circuit, configured for receiving the input signal and generating an intermediate signal correlated to the input signal; signal-selection means receiving the intermediate signal, the input signal, and providing an output signal which is the intermediate signal during the first operating condition, and the input signal during the second operating condition; and an input stage, connectable between the integrated circuit and the output terminal of the signal-selection means, configured for receiving the output signal and providing the output signal to the integrated circuit.

Communication cell for an integrated circuit, chip comprising said communication cell, electronic system including the chip, and test apparatus

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Rimini, Italy

Roberto Antonio Canegallo