Stmicroelectronics S.r.l.

Other

Roberto Annunziata

Paola Zuliani

Elisabetta Palumbo

Giovanni Campardo

Marina Scaravaggi

Marco MacCarrone

Jacopo Mulatti

Paolo Colombo

Daniele Zompi

Katia Giarda

A non-volatile memory device has a circuit branch associated to a bit line connected to a memory cell. When the memory cell is read, in a precharging step, the bit line is precharged. In a characteristic shift step, the memory cell is activated, and a current source is activated to supply a shift current to the first bit line and cause the bit line to charge or discharge on the basis of the datum stored in the memory cell. In a detection step, the current source is deactivated, the memory cell is decoupled, and the bit line is coupled to an input of a comparator stage that compares the voltage on the bit line with a reference voltage to supply an output signal indicating a datum stored in the memory cell.

Non-volatile memory device, in particular phase change memory, and reading method

A reference voltage generator for a matrix of non-volatile memory cells of the EEPROM type, comprises at least one array enabled by an access transistor. The array comprises at least one reference cell associated with a relative select transistor, the transistors and the cell being realized on a semiconductor substrate and having active regions delimited by suitable field oxide regions and covered by a tunnel oxide layer and comprising at least one floating gate realized by a first polysilicon layer and covered by a dielectric layer and by a second polysilicon layer. Advantageously, the floating gate of the reference cells is contacted by a first contact terminal connected to a discharge transistor for the periodical discharge of possibly present charges. A process manufactures such a voltage generator.

Reading voltage generator for a non-volatile EEPROM memory cell matrix of a semiconductor device and corresponding manufacturing process

A process for manufacturing a matrix of non volatile memory cells includes forming a floating gate transistor and a cell selection transistor in a first active area, and a byte selection transistor in a second active area. A multilayer structure is deposited, comprising a gate oxide layer, a first polysilicon layer, a dielectric layer, and a second polysilicon layer. The multilayer structure is defined to form two bands, the first band defining gate regions of the byte selection transistor and the cell selection transistor, and the second band defining the gate region of the floating gate transistor. A portion of the first band extends over a portion of insulating layer adjacent to the byte selection transistor. An opening is formed in the portion of the first band, exposing the first polysilicon layer, and a conductive layer is formed in the opening, electrically coupling the first polysilicon layer with the second polysilicon layer.

Process for manufacturing a byte selection transistor for a matrix of non volatile memory cells and corresponding structure

In a matrix of non volatile memory cells integrated on a semiconductor substrate, each memory cell includes a floating gate transistor and a selection transistor formed in a first active area, while each byte includes a byte selection transistor formed in a second active area separated from the first by portions of insulating layer. A portion of a multilayer structure including a gate oxide layer, a first polysilicon layer, a dielectric layer, and a second polysilicon layer extends over the byte selection and selection transistors, forming the gate regions thereof, and further extending on a portion of insulating layer. A conductive layer is formed in an opening in the second polysilicon and dielectric layers, over the portion of insulating layer, putting the first polysilicon layer in electric contact with the second polysilicon layer. Another portion of the multiplayer structure comprises the gate region of the floating gate transistor.

A process for fabricating high-voltage drain-extension transistors, whereby the transistors are integrated in a semiconductor substrate along with non-volatile memory cells that include floating gate transistors. The process includes: defining respective active areas for HV transistors and floating gate transistors in a semiconductor substrate, with the active areas separated from each other by insulating regions; forming insulated gate regions of the HV transistors; performing a first dopant implantation to form first portions of the HV transistor junctions; conformably depositing a dielectric layer onto the whole substrate to provide an interpoly layer of the floating gate transistor; making openings at the first portions of the HV transistor junctions; performing, through the openings, a second dopant implantation to form second portions of the high-voltage transistor junctions, with perimeter areas of the gate regions and the active area of the floating gate transistor being screened off by the dielectric layer.

Manufacturing process for a high voltage transistor integrated on a semiconductor substrate with non-volatile memory cells and corresponding transistor

An ESD protection network protects a CMOS circuit structure integrated in a semiconductor substrate. The circuit structure includes discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one primary voltage supply having a respective primary ground, and from at least one secondary voltage supply having a respective secondary ground. This network includes a first ESD protection element for an input stage of the circuit structure; a second ESD protection element for an output stage of the circuit structure, the first and second protection elements having an input/output pad of the integrated circuit structure in common; a first ESD protection element between the primary supply and the primary ground; and a second ESD protection element between the secondary supply and the secondary ground.

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Monza, Italy

Roberto Annunziata