Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Sgs-thomson Microelectronics Limited

Roberta Bottini

Bruno Vajana

Giovanna Dalla Libera

Carlo Cremonesi

Federico Pio

A process for manufacturing a semiconductor memory device includes double polysilicon level non-volatile memory cells and shielded single polysilicon level non-volatile memory cells in the same semiconductor material chip. A first memory cell includes a MOS transistor having a first gate electrode and a second gate electrode superimposed and respectively formed by definition in a first and a second layer of conductive material. A second memory cell is shielded by a layer of shielding material for preventing the information stored in the second memory cell from being accessible from the outside. The second memory cell includes a MOS transistor with a floating gate electrode formed simultaneously with the first gate electrode of the first cell by definition of the first layer of conductive material. The layer of shielding material is formed by definition of the second layer of conductive material.

Process for producing a semiconductor memory device comprising mass-storage memory cells and shielded memory cells for storing reserved information

A process for manufacturing a programmable non-volatile memory device having floating-gate MOS transistors, and first and second MOSFETs, the second MOSFETs capable of sustaining gate voltages higher than the first MOSFETs, by forming a first gate oxide layer for the floating-gate MOS transistors, a second gate oxide layer for the first MOSFETs, and a third gate oxide layer for the second MOSFETs. The process includes: forming a first oxide layer over a substrate; selectively removing the first oxide layer from surface regions over the first MOSFETs, but not from surface regions over the floating-gate MOS transistors or the second MOSFETs; forming a second oxide layer over the first oxide layer and the regions over the first MOSFETs; removing the first and second oxide layer from a tunnel oxide region of the floating-gate MOS transistors; and forming a tunnel oxide layer over the second oxide layer and tunnel region oxide layer.

Process for the manufacturing of an electrically programmable non-volatile memory device

A memory cell for devices of the EEPROM type, formed in a portion of a semiconductor material substrate having a first conductivity type. The memory cell includes source and drain regions having a second conductivity type and extending at the sides of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region, and a channel region extending between the region of electric continuity and the source region. The memory cell further includes an implanted region having the first conductivity type and being formed laterally and beneath the gate oxide region and incorporating the channel region.

Memory cell for EEPROM devices, and corresponding fabricating process

A process formes a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer depositing and partly defining a first polysilicon layer forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor depositing a second polysilicon layer selectively etching away the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor and selectively etching away the interpoly dielectric layer and the first polysilicon layer at the cell. After forming and before partially defining the first polysilicon layer, the process implants at least at the channel region of the floating-gate storage transistor for adjusting the transistor threshold.

Memory cell of the EEPROM type having its threshold adjusted by implantation, and fabrication method

A memory cell of the EEPROM type formed on a semiconductor material substrate having a first conductivity type includes a drain region having a second conductivity type and extending at one side of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region. The region of electric continuity is produced by implantation at a predetermined angle of inclination.

Memory cell for EEPROM devices and corresponding fabricating process

A process forms a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of, in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer; depositing and partly defining a first polysilicon layer; forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor; depositing a second polysilicon layer; selectively etching away, through a first mask, at least the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor; and selectively etching away, through a second mask, the interpoly dielectric layer and the first polysilicon layer at the cell. After the selective etch through said second mask, an implantation step is only carried out through the second mask and at least at the channel region of the floating-gate storage transistor to set the transistor threshold.

Memory cell of the EEPROM type having its threshold set by implantation, and fabrication method

Process for manufacturing of an integrated structure including at least one circuitry transistor and at least one non-volatile EEPROM memory cell with relative selection transistor, including at least a first stage of growth and definition of a gate oxide layer on a silicon substrate, a second stage of definition of a tunnel oxide region in said gate oxide layer, a third stage of deposition and definition of a first polysilicon layer on said gate oxide layer and on said tunnel oxide region, a fourth stage of growth and definition of an intermediate dielectric layer on said first polysilicon layer, a fifth stage of selective etching and removal of said dielectric intermediate layer in a region for said circuitry transistor, a sixth stage of ionic implantation of a dopant with a first type of conductivity in order to introduce said dopant into a channel region for said circuitry transistor in order to adjust its threshold voltage, a seventh stage of deposition and definition of a second polysilicon layer on said integrated structure, an eighth stage of selective etching and removal of said second polysilicon layer in a region for said memory cell, and of said first and second polysilicon layers in said region for said circuitry transistor in order to form said circuitry transistor, and a ninth stage of selective etching and removal of said intermediate dielectric layer and of said first polysilicon layer in said region for said memory cell, wherein during said fifth stage said intermediate dielectric layer is etched and removed also in a region that is destined to form a channel of said selection transistor, and said sixth stage of ionic implantation therefore allows to introduce said dopant into said channel region and therefore to increase the threshold voltage of said selection transistor.

EEPROM memory cell comprising a selection transistor with threshold voltage adjusted by implantation, and related manufacturing process

Process for manufacturing an electrically programmable non-volatile memory device having electrically programmable non-volatile memory cells comprising floating-gate MOS transistors, a first kind of MOSFETs, and a second kind of MOSFETs capable of substaining gate voltages higher than that sustainable by the MOSFETs of the first kind. The process includes forming a first gate oxide layer for the floating-gate MOS transistors, a second gate oxide layer for the MOSFETs of the first kind, and a third gate oxide layer for the MOSFETs of the second kind. The first gate oxide layer further comprises a tunnel oxide region. The process provides for: forming over the surface of a semiconductor material a first layer of oxide; selectively removing the first layer of oxide from regions of said surface dedicated to the MOSFETs of the first kind, but not from the regions dedicated to the floating-gate MOS transistors nor to the MOSFETs of the second kind; forming a second layer of oxide over the first layer of oxide and over said regions dedicated to the MOSFETs of the first kind; simultaneously removing the first and the second layer of oxide only from the tunnel oxide region of the floating-gate MOS transistors; and forming over the second layer of oxide and over said tunnel region oxide for the floating-gate MOS transistors a tunnel oxide layer. The third gate oxide layer and said first gate oxide layer, except in the tunnel oxide region, are formed by the superposition of the first layer of oxide, while the second layer of oxide and the tunnel oxide layer, said second gate oxide layer being formed by the superposition of the second layer of oxide and the tunnel oxide layer.

A process for fabricating a memory cell having two levels of polysilicon and being included in a memory device of the EEPROM type, wherein the device is formed on a semiconductor material substrate which has a first conductivity type. The process comprises the steps of forming, on the substrate a thin tunnel oxide region surrounded by a gate oxide region previously formed on the same substrate, depositing a layer of polycrystalline silicon over the gate oxide region and the thin tunnel oxide region, and successively depositing a composite ONO layer and an additional polysilicon layer over the polycrystalline silicon layer. A capacitive implant mask having a window is formed by depositing a layer of a light-sensitive material over the additional polysilicon layer, a dopant is implanted through the window at an energy and with dosages effective to penetrate the polycrystalline silicon, ONO, and polysilicon layers, respectively, and a region of electric continuity is formed laterally and beneath the thin tunnel oxide region.

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Lissone, Italy

Roberta Bottini