Sun Microsystems, Inc.

Intel Corporation

Other

Agilepower Systems, Inc.

Robert Zak

Christopher J Jackson

James Dinan

Thomas D Lovett

David Pardo Keppel

Michael A Parker

Monica C Wong-Chan

Jon P Wade

Mark Donald Hill

David Allen Wood

Mario Flajslik

Gary S Muntz

Thomas P Webber

Chung-Hsiao Wu

Sayantan Sur

Andrew Friedley

Hien H Nguyen

Maria Garzaran

Nusrat Islam

Anupama Kurpad

An embodiment of a semiconductor package apparatus may include technology to embed one or more trigger operations in one or more messages related to collective operations for a neural network, and issue the one or more messages related to the collective operations to a hardware-based message scheduler in a desired order of execution. Other embodiments are disclosed and claimed.

Triggered operations to improve allreduce overlap

Technologies for Ethernet gateway congestion management in HPC architectures include a high-performance computing (HPC) switch with an Ethernet gateway that is configured to receive an HPC packet from an HPC fabric via a virtual lane (VL) of the Ethernet gateway. The Ethernet gateway is further configured to determine whether the HPC packet corresponds to a backward error correction notification (BECN), identify one or more priority code points (PCPs) of the HPC packet corresponding to a BECN as a function of the VL on which the HPC packet was received, and generate an Ethernet priority-based flow control (PFC) frame that includes the one or more identified PCPs in a header of the Ethernet PFC frame. Additionally, the Ethernet gateway is configured to transmit the Ethernet PFC frame to an Ethernet fabric as a function of the one or more identified PCPs. Other embodiments are described herein.

Technologies for ethernet gateway congestion management in high-performance computing architectures

Particular embodiments described herein provide for a network element that can be configured to receive a request message, wherein the request message includes a read trigger, an indicator selector, and a completion trigger, determine an indicator that relates to the indicator selector, and perform an action when the read trigger is activated.

Performance monitoring

Technologies for endpoint congestion avoidance are disclosed. In order to avoid congestion caused by a network fabric that can transport data to a compute device faster than the compute device can store the data in a particular type of memory, the compute device may in the illustrative embodiment determine a suitable data transfer rate and communicate an indication of the data transfer rate to the remote compute device which is sending the data. The remote compute device may then send the data at the indicated data transfer rate, thus avoiding congestion.

Technologies for endpoint congestion avoidance

Technologies for tracing network performance include a network computing device configured to receive a network packet from a source endpoint node, process the received network packet, capture trace data corresponding to the network packet as it is processed by the network computing device, and transmit the received network packet to a target endpoint node. The network computing device is further configured to generate a trace data network packet that includes at least a portion of the captured trace data and transmit the trace data network packet to the destination endpoint node. The destination endpoint node is configured to monitor performance of the network by reconstructing a trace of the network packet based on the trace data of the trace data network packet. Other embodiments are described herein.

Technologies for sideband performance tracing of network traffic

A reciprocating internal combustion engine is based on Homogenous Charge Compression Ignition (HCCI) that occurs in a deformable, resonant combustion chamber and that is coupled mechanically to efficient, resonant, electro-mechanical transducers acting as motors and generators. The mechanical coupling also implements fuel/air intake valves and exhaust valves. Embedded sensors allow an electronic control system to start the engine and thereafter to maintain operational configuration of the moving components in response to the effects of imperfect mechanical fabrication and/or assembly and dynamic changes in mechanical properties of the materials with run-time temperature and engine life.

Deformable chamber-based homogeneous charge combustion ignition (HCCI) engine and generator

A method and apparatus for controlling a DRAM refresh rate. In one embodiment, a computer system includes a memory subsystem having a memory controller and one or more DRAM (dynamic random access memory) devices. The memory controller is configured to periodically initiate a refresh cycle to the one or more DRAM devices. The memory controller is also configured to monitor the temperature of the one or more DRAM devices. If the temperature exceeds a preset threshold, the memory controller is configured to increase the rate at which the periodic refresh cycle is performed.

Variable memory refresh rate for DRAM

An apparatus and method for resending a request in a computer system using a delay value is provided. In response to receiving a request, a target device in a computer system may detect that it is temporarily unable to process the request. The target device can send a response to the sending device to indicate that it is temporarily unavailable. The response can include a delay value that can provide a hint to the sending device as to when to resend the request. The target device may generate the delay value according to the type of condition that is causing it to be temporarily unavailable. The delay value may be generated according to a static heuristic or a dynamic algorithm based on previous temporarily unavailable conditions. The delay value may also be used by an error recovery mechanism where a sending device exceeds a retry limit for a particular request.

System and method for enhancing communication between devices in a computer system

Deformable combustion chamber-based internal combustion engine and generator

A method and device for off-loading from an application program the calculation of a data-integrity-checking value for specified data in a computer system. The data may be included in a message together with the integrity-checking value or may be in a portion of a memory window for direct memory access. The method includes communicating a selected data-integrity-checking scheme from a specified set of schemes to another processor to off-load calculation of the data-integrity-checking value. A related method associates a message to be received with a data-integrity-checking scheme, so that a receiving processor can calculate the data-integrity-checking value and transmit both the value and the message to another processor.

Method and device for off-loading message digest calculations

A method and mechanism for annotating a transaction stream. A processing unit is configured to generate annotation transactions which are inserted into a transaction stream. The transaction stream, including the annotations, are subsequently observed by a trace unit for debug or other analysis. In one embodiment, a processing unit includes a trace address register and an annotation enable bit. The trace address register is configured to store an address corresponding to a trace unit and the enable bit is configured to indicate whether annotation transactions are to be generated. Annotation instructions are added to operating system or user code at locations where annotations are desired. In one embodiment, annotation transactions correspond to transaction types which are not unique to annotation transactions. In one embodiment, an annotation instruction includes a reference to the trace address register which contains the address of the trace unit. Upon detecting the annotation instruction, and detecting annotations are enabled, the processing unit generates an annotation transaction addressed to the trace unit. In one embodiment, annotation transactions may be used to indicate context switches, processor mode changes, timestamps, or address translation information.

Annotations for transaction tracing

A system and method for performing a sync operation for multiple devices in a computer system is provided. The computer system may include a plurality of devices and a plurality of agents. The agents may be configured to perform tasks on behalf of the devices. A busy bit and a counter may be included for each of the agents. One of the devices may become an observer by initiating a sync operation. In response to a sync operation, busy agents may be identified using the busy bit for each agent. The busy agents may then be monitored to determine when each one has cycled using the busy bit and the counter for each busy agent. A busy agent may be determined to have cycled in response to its busy bit indicating that it is no longer busy or in response to its counter value differing from the counter value at the time the sync operation was initiated. Once each of the busy agents have cycled, the observer may determine that the sync operation is complete.

System and method for performing a synchronization operation for multiple devices in a computer system

A performance counter to monitor a plurality of events that may occur in a component within a computer system during a monitoring period or testing period. The monitoring results, which are provided upon completion of the performance testing, may be used to provide histogram representations of the component performance. In one embodiment, the performance counter comprises a first storage, a second storage, programmable control logic, and a counting mechanism. The first storage is configured to store information indicative of a plurality of events to be monitored and the monitoring period for each event. The second storage is configured to store counting results obtained during the testing period. A counting mechanism, which is coupled to the second storage, is configured to monitor the occurrence of the events in the component under test. The counting mechanism is coupled to the control logic and the control logic is coupled to the first storage.

Growing community of inventors

Bolton, MA, United States of America

Robert Zak