Sun Microsystems, Inc.

Robert Yung

Timothy J Van Hook

Leslie Dean Kohn

William N Joy

Marc R Tremblay

Neil C Wilhelm

Leslie D Kohn

Charles E Narad

Michael R Allen

Robert F Sproull

Sun-den Chen

Stephen K Howell

Thomas L Lyon

Jaijiv Prabhakaran

Greg Williams

Guillermo Maturana

Carlan Joseph Beheler

Kit Sang Tam

Alfred K W Yeung

Huoy-Ming Yeh

An image processor converts single-band pixel components, each of which represents a single band of a multiple-band pixel, to multiple-band pixels. A embodiment, a single read operation reads four single-band pixel components from each of three buffers which correspond to red, green, and blue bands, respectively, of a multiple-band graphical image. A single merge operation merges eight single-band pixel components representing alpha and green bands of four multiple-band pixels, and a single merge operation merges eight single-band pixel components representing blue and red bands of four multiple-band pixels. Two merge operations merge the respective merged data words to form four multiple-band pixels, each of which includes alpha, blue, green, and red components. The four multiple-band pixels are written to a destination buffer in four write operations.

Graphical image data reformatting method and apparatus

An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer and floating point operations. A number of specialized graphics instructions and accompanying hardware for executing them are disclosed to optimize the execution of graphics instruction with minimal additional hardware for a general purpose CPU.

Microprocessor with parallel inverse square root logic for performing graphics function on packed data elements

The invention relates to a computer system and method for fetching a next instruction. In one embodiment, a computer system includes an instruction cache, a next fetch address register, and a fetch unit. The instruction cache includes an instruction array for storing a plurality of processor instructions and a next address fetch array for storing at least one next fetch address. Each next fetch address associated with at least one of the processor instructions stored in the instruction array and indicating a location of a processor instruction to be fetched. In another embodiment, an apparatus includes a first device configured to fetch a first instruction stored in an instruction cache, a second device configured to unconditionally store a next fetch address associated with the first instruction, and a third device configured to unconditionally fetch a second instruction stored at a location indicated by the stored next fetch address.

Computer system and method for fetching a next instruction

An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer floating point operations is provided. Independent execution paths are provided for different graphics instructions to allow parallel execution of instructions which commonly occur together. The invention also optimizes the use of register file accesses to avoid, as much as possible, interference between graphics instructions needing to access a register file and other instruction accesses which would occur in combination with graphics instructions, thereby avoiding pipeline stalls and allowing parallel execution.

Central processing unit with integrated graphics functions

The present invention provides an efficient streamlined pipeline for a counterflow pipeline processor with a renaming table. The counterflow pipeline includes an execution pipe having multiple instruction stages forming an instruction pipe, a plurality of result stages forming a result pipe, and a corresponding plurality of comparator/inserters. Each comparator/inserter couples an instruction stage to a corresponding result stages. The counterflow pipeline also includes a register exam stage with the renaming table. The renaming table has entries for associating each register value of an instruction with a unique renamed register number (RRN), thereby eliminating the need for arbitration and housekeeping (killing of stale register values), as instructions and their respective register values counterflow in the streamlined counterflow pipeline. An RRN counter, such as a modulo counter, is coupled to the renaming table and provides unique RRNs for assignment to new register values. In accordance with one embodiment of the invention, instructions are decoded and unique RRNs assigned to the source and destination operand registers. If there is no previous RRN assigned to a register operand, its register value is retrieved from a register file and inserted into the top of the result pipe. In addition, when an instruction execution produces a register result value in the execution pipe, the associated RRN and register value are inserted laterally into the result pipe. The register values and RRNs, in the form of result packages, are garnered by younger (later in program order) instructions counterflowing up the instruction pipe.

Instruction result labeling in a counterflow pipeline processor

A processor method and apparatus. The processor has an execution pipeline, a register file and a controller. The execution pipeline is for executing an instruction and has a first stage for generating a first result and a last stage for generating a final result. The register file is for storing the first result and the final result. The controller makes the first result stored in the register file available in the event that the first result is needed for the execution of a subsequent instruction. By storing the result of the first stage in the register file, the length of the execution pipeline is reduced from that of the prior art. Furthermore, logic required for providing inputs to the execution pipeline is greatly simplified over that required by the prior art.

Temporary pipeline register file for a superpipelined superscalar

Partitioned multiply and add/subtract instruction for CPU with

A processor is disclosed. The processor includes a processing unit with a plurality of pipelines. Each of the pipelines execute instructions which may define source register values and destination register values from a register file. A plurality of memories is also provided, each associated with one of the plurality of pipelines respectively. A coherency mechanism is provided to maintain coherency among the register values in the plurality of pipelines and their associated memories. In one embodiment, each memory associated with the plurality of pipelines is a register cache. Each register cache stores register values that were just used or will soon be needed by the instructions that have or will be executed on the pipeline associated with the register cache. A variety of coherency mechanisms may be used to transfer register values from register cache to register cache and maintain coherency among the register values in the plurality of register caches. The coherency protocols include, but are not limited to ownership protocols, snooping protocols and a new protocol that permits only one addressable valid copy of a register value among all the register caches and the register file at a time.

Processor having a plurality of pipelines and a mechanism for

The integer execution unit (IEU) of a central processing unit (CPU) is provided with a graphics status register (GSR) for storing a graphics data scaling factor and a graphics data alignment address offset. Additionally, the CPU is provided with a graphics execution unit (GRU) for executing a number of graphics operations in accordance to the graphics data scaling factor and alignment address offset, the graphics data having a number of graphics data formats. In one embodiment, the GRU is also used to execute a number of graphics data addition, subtraction, rounding, expansion, merge, alignment, multiplication, logical, compare, and pixel distance operations. The graphics data operations are categorized into a first and a second category, and the GRU concurrently executes one graphics operations from each category. Furthermore, under this embodiment, the IEU is also used to execute a number of graphics data edge handling and 3-D array addressing operations, while the load and store unit (LSU) of the CPU is also used to execute a number of graphics data load and store operations, including conditional store operations.

A partial store instruction and associated logic for storing selected bytes of a group of bytes in a register to a designated memory location. A mask in a separate register is used to enable particular bytes to be written, with only enabled bytes being written to the final location. The mask can be previously generated as a result of a comparison or other operation. The creation of the mask and the execution of a partial store instruction can also be used as a prefetch instruction, eliminating the need for a separate opcode for a prefetch.

Graphic system for masking multiple non-contiguous bytes having decode

A cache structure for a microprocessor which provides set-prediction information for a separate, second-level cache, and a method for improving cache accessing, are provided. In the event of a first-level cache miss, the second-level set-prediction information is used to select the set in an N-way off-chip set-associative cache. This allows a set-associative structure to be used in a second-level cache (on or off chip) without requiring a large number of traces and/or pins. Since set-prediction is used, the subsequent access time for a comparison to determine that the correct set was predicted is not in the critical timing path unless there is a mis-prediction or a miss in the second-level cache. Also, a cache memory can be partitioned into M sets, with M being chosen so that the set size is less than or equal to the page size, allowing a cache access before a TLB translation is done, further speeding the access.

Microprocessor having a cache memory system using multi-level cache set

A microprocessor with a dispatch unit which dispatches a maximum number of instructions each cycle, without splitting into separate blocks after a branch instruction. A mispredicted branch is handled by setting a valid bit to invalid for instructions following the branch instruction in an outstanding instruction FIFO.

Multiple instruction dispatch system for pipelined microprocessor

A processor is disclosed. The processor relates to a processor having a register file of registers and a dispatch unit capable of issuing up to (i) instructions of a program per cycle to an execution unit having (z) pipelines, wherein some of the instructions specify certain ones of the registers in the register file as source operands and designate certain ones of the registers in the register file as destination registers. The processor also includes a memory for storing the registers of the register file, the memory having (N) access ports configured to access up to (N) registers per cycle, where (N) is less than a maximum number of register values that may need to be accessed during a cycle.

Computer processor having a register file with reduced read and/or write

A computer system which includes a processor having an instruction set capable of 'delaying' block-store instructions related to any outstanding block-load instruction(s). Accordingly, a method for interleaving block data transfers and processing steps which exploits the characteristics of the instruction set and architecture of the processor in order to increase efficiency and throughput of the computer system is provided. Hence by interleaving the block-store instruction of the previous data block with the block-load instruction of the next data block, the entire block transfer process can streamlined.

Growing community of inventors

Fremont, CA, United States of America

Robert Yung