Lucent Technologies Inc.

Agere Systems Inc.

At+t Corp.

Agere Systems Guardian Corp.

Robert William Walden

Steven R Norsworthy

David Arthur Rich

Ramin Khoini-Poorfard

Krishnaswamy Nagaraj

Maarten Visee

Bruce W McNeill

David G Martin

Richard Verney

Rogelio Peon

William Edward Burchanowski

Stephen H Lewis

Ignacio Herrera Alzu

A circuit for, and method of, detecting a signal level on a node and a mobile telephone device incorporating the circuit or the method. In one embodiment, the circuit includes: (1) a switch coupled between a voltage source and the node, (2) a pulse generator coupled to the switch and configured to generate a pulse to control the switch and (3) a detection circuit coupled to the node and configured to detect a signal level at the node on closure of the switch.

Low-power switch state detection circuit and method and mobile telephone incorporating the same

A method and apparatus for selecting and mixing electronic signals. The circuit has an operational amplifier and two or more ganged, tapped-resistors in which the tap divides the resistance into a first and a second resistance. The tapped-resistors are connected so that either the first or the second resistance provides the effective input resistance for that signal at the operational amplifier. The second resistance of one of the tapped-resistors provides the output resistance for all signals at operational amplifier. As the tapped resistors are equivalent and their taps ganged, when the signals are mixed, those signals whose effective input resistance at the operational amplifier is selected to be the second resistance have unit gain, while those signals whose effective input resistance at the operational amplifier is selected to be the first resistance have a gain equal to the second resistance divide by the first resistance.

Multi-input gain control circuit

A recurring noise filter for removing from a signal noise generated by parasitic coupling from a switching network. The filter contains an input filter, a sampling switch and an output filter. The input filter is a low pass filter which receives a signal containing noise generated by parasitic coupling from a switching network. The sampling switch is connected between the low pass filter and an output filter, with the sampling switch activating in response to the recurring switching of said switching network to sample the signal during the interval at which said noise does not occur within the signal. The output filter removes signals generated by the sampling switch from the sampled signal thereby generating a noise-filtered signal.

Filter to remove noise coupling into a sensitive circuit node

A method and apparatus are provided for matching the primary and parasitic capacitances of integrated circuit capacitors. The integrated circuit capacitors to be matched in accordance with the present invention can be of different sizes and connected in different circuit topologies. For example, the matching filter can have a differential filter capacitor structure and the reference circuit can have a single-ended filter configuration (or vice versa). The reference circuit to be matched is initially analyzed to identify the ratio of the primary capacitance, C , to the parasitic capacitance, C . Thereafter, a matching filter is selected with the desired topology and having the same ratio of the primary capacitance, C , to the parasitic capacitance, C , as the reference circuit (or a desired offset therefrom). A general technique is disclosed for analyzing capacitance circuits to identify the ratio of the primary capacitance, C , to the parasitic capacitance, C .

Method and apparatus for matching capacitance of filters having different circuit topologies

An amplifier architecture wherein a primary or main operational amplifier is combined with a secondary or auxiliary high power operational amplifier to maintain the charge on a large load capacitor which operates as voltage reference source for a high precision analog circuit module. The auxiliary amplifier is activated only during brief periods for which a very high slew rate is required. This is achieved by additionally including a control circuit which regulates the operation of the auxiliary amplifier so that it operates only during very short intervals of very high load while the main operational amplifier accommodates all other normal operating conditions.

High slew-rate operational amplifier architecture

An integrated circuit includes an oscillator circuit for generating an output signal having a desired frequency. The oscillator circuit includes a capacitive device having a controllable capacitance value responsive to a control signal. A control circuit is connected to the oscillator circuit for controlling the capacitance value so that the oscillator circuit generates the output signal at the desired frequency. The control circuit includes a memory for storing a digital control word and a control signal generating circuit for converting the digital control word into the control signal for the capacitive device. Setting the desired frequency of the output signal is performed internal to the integrated circuit without requiring complex control circuitry for switching among various capacitors.

Integrated oscillator circuit with a memory based frequency control circuit and associated methods

An integrated transconductor circuit has an active load element and two parallel sets of transconductor stages. The active load element provides a high impedance without requiring a large area within the integrated transconductor circuit, and provides linear impedance when the active load devices are biased in the triode region of their respective characteristic curves. The multiple transconductor stages prevent saturation from reducing the dynamic range available at the output of the transconductor circuit. The parallel sets of transconductor stages are used to improve output linearity by reducing the differences between the threshold voltages of the serially-connected transconductor stages. In a particular example, the sizes of the active devices of the sets of transconductor circuit stages are chosen to provide a monotonic, substantially exponential transconductance to implement a control input to a current-controlled oscillator in a phase-locked loop that assures the frequency-independent stability of the phase-locked loop. The exponential function is selectively rolled off at the upper end to prevent excessively high-frequency operation at start-up from over-driving a divider logic and locking up the phase-locked loop. The transfer function curve of the transconductor circuit is robust to process variations over a wide range of operating conditions.

Linear CMOS transconductor with rail-to-rail compliance

A bandgap voltage reference circuit for 0.35-.mu.m, 3-volt CMOS technology operates in an essentially temperature independent manner and having low supply voltages. The bandgap voltage reference circuit incorporates two operational amplifiers. One operational amplifier biases bipolar devices of the circuit and generates a PTAT voltage across a resistor, and the other operational amplifier buffers a voltage related to the PTAT voltage and a voltage across one bipolar device to generate the bandgap voltage reference. In one embodiment, the circuit includes a start-up circuit to ensure a stable and desired start-up state. A current bias may also be provided. The bandgap voltage reference of the second operational amplifier may also provide a regulated supply for the first stage of the circuit. The second operational amplifier also provides a buffered output to a resistor divider circuit to supply a voltage divider to generate voltages below the 1.24-volt bandgap voltage. The bandgap voltage reference circuit includes two versions, one which is optimized for a low supply voltage potential V.sub.DD of approximately 1.8 volts and the other for a standard supply voltage V.sub.DD of approximately 2.4 volts.

CMOS bandgap voltage reference

A method and system for a clock driver is described which can buffer an master clock directly, or generate a output clock signal having a balanced duty cycle which is the input clock frequency divided by a predetermined value. When a frequency control input, such as a rate signal, is switched, the clock output makes a glitchless transition from one frequency to the other. The clock driver includes a counter divider circuit with feedback to produce two signals related by a predetermined phase difference. The counter divider circuit employs predetermined logic delays by buffered gating controlled by the master clock, which produces two signals. These two signals act as 'enable' control signals such that the timing of their rising and falling edges is arranged to never propagate through the clock divider circuit to become the edges of output clock. The master clock is gated with these two signals to provide two unbalanced signals which are synchronous to the input clock signal. In addition, these two unbalanced signals have waveforms such that they may then be logically combined to form a single, balanced signal in a glitchless manner. Furthermore, transitions between fast, slow, and disable modes of operation for such clock driver circuit are also synchronous with the master clock and glitchless.

Divide-by-one or divide-by-two qualified clock driver with glitch-free

A level shifter circuit which is suitable for use in an integrated circuit converts an input logic signal having a first voltage potential to an output logic signal having a second voltage potential. For logic signals transmitted between sections of an integrated circuit operating with different supply voltages, the level shifter circuit allows reliable circuit operation between the sections when the voltage potential of the input logic signal is converted to the output logic signal having a higher voltage potential, the same voltage potential, or a lower voltage potential. The level shift circuit includes an inverter stage which drives a fully differential output stage, and the fully differential output stage includes two sections. Each section incorporates a fast switching pair of transistors connected in series across an output supply voltage and ground potential which act as an inverter and which provide an output node at the series connection. For a section, the series-connected transistor between the output supply voltage and the output node is also connected in parallel with a voltage pull-up transistor having its gate controlled by the signal provided at the output node of the other section. The first section is controlled by the input logic signal provided to the gate of the series-connected transistor between its output node and the ground potential and the inverted input logic signal provided to the gate of the series-connected transistor between its output node and the output supply voltage. Similarly, the second section is controlled by the inverted input logic signal provided to the gate of the series-connected transistor between its output node and the ground potential and the input logic signal provided to the gate of the series-connected transistor between its output node and the output supply voltage.

Universal logic level shifting circuit and method

Testing of digital-to-analog converters is accelerated by applying one or more different approaches. One approach relies on a switched capacitor, which lowers the overall capacitance of the converter during testing, thereby reducing the settling time for each code value. Another approach makes the duration of each testing step a function of the particular code value, rather than using the worst-case settling time for each testing step. Yet another approach uses a sequence of non-consecutive code values to determine whether each switch in the converter is functional. Using non-consecutive code values permits the use of partial settling times during converter testing. Each of the approaches can be used to accelerate the testing of D/A converters, whether they have linear or folded resistor strings.

Fast testing of D/A converters

A device comprises: an analog-to-digital converter; a digital signal processor; a digital dither signal generator; and a signal coupling device adapted to selectively couple one of the dither signal generator and the digital signal processor to the signal path in the converter. A method of testing a dithered analog-to-digital converter employing an M-bit digital signal generator, M being a positive integer, comprises the steps of: generating an M-bit, periodic signal; providing the generated signal to the dithered converter at a point along the signal path of the dithered converter in place of the dither signal; and measuring the digital output signal produced by the converter.

Circuit and method for testing a dithered analog-to-digital converter

A circuit which detects the median peak of a burst of pulses. The peak value of each pulse in a pulse burst is detected and stored. The peak value of each pulse is then compared to the peak value of every other pulse and the results of the comparison are used to determined the median peak.

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Bethlehem, PA, United States of America

Robert William Walden