Lucent Technologies Inc.

At&t Bell Laboratories

Agere Systems Inc.

Robert William Ryan

Rose Fasano Kopf

Robert Alan Hamm

Alaric Tate

Jinwook Burm

Roger J Malik

Leda M Lunardi

Yu-Chi Wang

Christopher James Pinzone

A method of fabricating a III-V heterostructure semiconductor device. The method includes the steps of forming at least one conductive post overlying a semiconductor region to form a structure, encapsulating the structure and the conductive post to form a planarized cured passivation layer, and exposing the conductive post through the planarized cured passivation layer to form the semiconductor device.

Method of fabricating a heterojunction bipolar transistor

The specification describes a lithographic technique in which alignment marks are defined in a first semiconductor layer and the alignment marks are then covered with a protective SiO,layer. After subsequent semiconductor layer growth steps, which selectively deposit on the former semiconductor layer but not on the protective layer, the alignment marks remain undistorted and visible to the exposure tool for subsequent processing.

Alignment techniques for epitaxial growth processes

The specification describes a metal contact material optimized for diffused contacts to the buried emitter-base junction in DHBT devices. The metal contact material is a multilayer structure of Pd--Pt--Au which gives the required critical diffusion properties for low resistance contacts to the buried base layer without shorting to the collector layer.

Method for making InP heterostructure devices

The specification describes a trilevel resist technique for defining metallization patterns by lift-off. The trilevel resist comprises two standard photoresist levels separated by a thin silicon oxide layer with approximate composition SiO.sub.2.

Trilayer lift-off process for semiconductor device metallization

The specification describes a photolithography process using multiple exposures to form z-dimension patterns. Multiple exposures at different thickness levels are made using photomasks aligned with a latent image of alignment marks formed during the first exposure. The latent image is visible to the alignment system of commercial steppers.

Method of manufacturing schottky gate transistor utilizing alignment

Alignment techniques for photolithography utilizing multiple photoresist

The specification describes a technique for repairing wafer fractures that occur during wafer fabrication. The fractured pieces are joined edge-to-edge at the fracture line and bonded with epoxy adhesive. The method succeeds because the dimensions of the fracture line after bonding is within the reregistration tolerance of commercial step-and-repeat cameras and the reregistration capability of the camera allows normal exposure of sites that do not intersect the fracture line.

Repairing fractured wafers in semiconductor manufacturing

The specification describes a metal contact material optimized for diffused contacts to the buried emitter-base junction in DHBT devices. The metal contact material is a multilayer structure of Pd-Pt-Au which gives the required critical diffusion properties for low resistance contacts to the buried base layer without shorting to the collector layer.

INP heterostructure devices

A novel method of making a semiconductor device that comprises p-type III-V semiconductor material is disclosed. The method comprises heating of a graphite body such that the body serves as a sublimation source of carbon atoms that are incorporated into the III-V semiconductor material. Exemplarily, the carbon doped material is the base of a GaAs-based HBT.

Method of making a semiconductor device that comprises p-type III-V

A scalable and relatively easily manufacturable heterojunction bipolar transistor (HBT) comprises a thin (exemplarily 5-25 nm) emitter layer that serves as an etch stop layer and that furthermore passivates the extrinsic base region. The portion of the emitter layer that overlies the extrinsic base region is essentially fully depleted at all bias voltages in the normal operating range of the transistor. Base contact is established through the emitter layer, exemplarily by means of a metallized region on the emitter layer. A novel technique for carbon doping is also disclosed. Use of the novel technique makes possible a further embodiment of the inventive HBT, wherein base contact is made by means of Be implantation into the emitter layer.

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Piscataway, NJ, United States of America

Robert William Ryan