International Business Machines Corporation

Robert William Hay

Balaram Sinharoy

James Allan Kahle

Lee Evan Eisen

John Edward Derrick

Hung Qui Le

David S Levitan

Paul Joseph Jordan

Brian R Konigsburg

Roch Georges Archambault

Ronald Ian McIntosh

James Lawrence McInnes

Robert F Enenkel

Allan Russell Martin

Mark Peter Mendell

A method, apparatus, and computer instructions for processing instructions. A data dependency graph is built. The data dependency graph is analyzed for recurrences, and unpipelined instructions that lie outside of the recurrences are expanded.

Method and apparatus for determining the profitability of expanding unpipelined instructions

A field is defined in branch instructions which is interpreted by software as &ldquo;Hint&rdquo; bits and these bits are used to signal the processor of special circumstances that may arise when doing speculative branch instruction execution to enable better branch address prediction accuracy and a reduction in link stack corruption which improves overall execution times. A programmer or compiler determines if a branch instruction usage fits in the context for a Hint action. If so, the compiler or programmer, using assembly/machine language, sets Hint bits in the branch instruction when it is compiled. If the branch is later speculatively executed, the processor decodes the Hint bits and executes and a hardware action corresponding the decode of the Hint bits. These Hints include four specific Hint actions, however, the field reserved for Hint bits is five bit wide reserving up to thirty-two specific Hint cases may be specified. These Hint cases (or Hint bits) may be interpreted differently for each type of branch instruction supported.

Software hint to improve the branch target prediction accuracy

A method and system is disclosed for software manipulation of hardware prediction mechanism in a data processor with software prediction. The hardware branch prediction mechanism is enhanced with at least two bits for path prediction. These bits are settable by a software and are capable of overriding the hardware branch prediction mechanism. Branch prediction information is encoded into a branch instruction in the software. This information includes a pre-determined value for each bit. Finally, a branch path of said instruction is predicted based on the value of the bits.

Method and system for software control of hardware branch prediction mechanism in a data processor

An XER scoreboard function is provided by utilizing the instruction sequencer unit scoreboard. A scoreboard bit is set if the XER is being used by a previous instruction. If a new instruction is fetched that uses the XER, a dummy read to the XER is generated to test the scoreboard bit to determine if the scoreboard bit is set. If the scoreboard bit is not set when the dummy read is executed, the X-form string proceeds to execution. If the scoreboard bit is set when the dummy is executed, the pipeline is stalled until the scoreboard bit is cleared, and then the X-form string padded with generated padding IOPs (Dummy or NOPs) is executed. After an accessing instruction is executed, the scoreboard bit is cleared.

Scoreboard mechanism for serialized string operations utilizing the XER

A method and system for aligning internal operations (IOPs) for dispatch are disclosed. The method and system comprise conditionally asserting a predecode based on a particular dispatch slot that an instruction is going to be placed. The method and system further include using the information related to the predecode to expand an instruction into at least one dummy operation and an IOP operation whenever the instruction would not be supported in the particular dispatch slot.

System and method for utilizing a conditional split for aligning internal operation (IOPs) for dispatch

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Austin, TX, United States of America

Robert William Hay