Gallitzin Allegheny LLC

Other

Intellectual Ventures I LLC

Robert Warren Sherburne, Jr

Dominik J Schmidt

In one embodiment of the present invention, a processor includes a scalar computation unit; a vector co-processor coupled to the scalar computation unit; and one or more function-specific engines coupled to the scalar computation unit, where the engines are adapted to minimize data exchange penalties by processing small in-out bit slices.

Methods and apparatus for processing scalar and vector instructions

A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; one or more clock controllers having clock outputs coupled to the clock inputs of the processing units, the controller operating varying the clock frequency of each processing unit to optimize speed and processing power for a task; and a high-density memory array core coupled to the processing units.

Clocking system including a clock controller that uses buffer feedback to vary a clock frequency

A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; and a controller having a plurality of clock outputs each coupled to a respective clock input of one of the processing units, the controller varying the clock frequency of each processing unit to optimize power consumption and processing power for a task.

Low power clocking systems and methods

A low power a reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; and a controller having a plurality of clock outputs each coupled to the clock inputs of the processing units, the controller varying the clock frequency of each processing unit to optimize power consumption and processing power for a task.

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Kentfield, CA, United States of America

Robert Warren Sherburne, Jr