Lsi Corporation

Micron Technology Incorporated

Seagate Technology Incorporated

Agere Systems Inc.

Seagate Technologies, Inc.

Robert Warren

Danilo Caraccio

Daniele Balluchi

Victor Y Tsai

Neal Anthony Galbo

Brian Dennis McKean

Robb Mankin

Steven Scott Williams

Jackson L Ellis

Kian Keong Ooi

Kendall Hayne Fung

Edward Sean Hoskins

Eskild Thormod Arntzen

Wayne Lawrence Buckholdt

Lucas KongYaw Lee

Sheri L Fredenberg

Lai Kein Chang

Buddy Scott Holt

David G Dalton

Brian Nollinger Nollinger

Nikolai K Bahram

Fadi Afa Al-Refaee

Stephen N Haddad

Danilo Carracio

The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

Command queuing

Various embodiments of the present invention provide systems and methods for managing solid state drives. As an example, a storage system is described that include at least a first flash memory block and a second flash memory block, and a control circuit. The first flash memory block and the second flash memory block are addressable in the storage system. The control circuit is operable to identify the first flash memory block as partially failed, receive a write request directed to the first flash memory block; and direct the write request to the second flash memory block.

Systems and methods for managing end of life in a solid state drive

An apparatus comprising a magnetic media and a read/write unit. The magnetic media may be configured to store data. The magnetic media may also be rotated during access of the magnetic media. The read/write unit may comprise a plurality of transducers arranged in a linear array. Each of the transducers may be fabricated on a semiconductor substrate with fixed head positions with respect to the magnetic media. The read/write unit may also be positioned in close proximity to and across the surface of the magnetic media. Each transducer may be configured to read data from the magnetic media and write data to the magnetic media.

Ultra fast disk access using arrays of fixed read/write transducers

Various embodiments of the present invention provide systems, methods and circuits for use of a memory system. As one example, an electronics system is disclosed that includes a memory bank, a memory access controller circuit, and an encoding circuit. The memory bank includes a plurality of multi-bit memory cells that each is operable to hold at least two bits. The memory access controller circuit is operable to determine a use frequency of a data set maintained in the memory bank. The encoding circuit is operable to encode the data set to yield an encoded output for writing to the memory bank. The encoding level for the data set is selected based at least in part on the use frequency of the data set.

Systems and methods for variable level use of a multi-level flash memory

Various embodiments of the present invention provide systems, methods and circuits for memories and utilization thereof. As one example, a memory system is disclosed that includes a flash memory device and a flash access circuit. The flash access circuit is operable to perform an error code encoding algorithm on a data set to yield an error code, to write the data set to the flash memory device at a first location, and to write the error code to the flash memory device at a second location.

Systems and methods for re-designating memory regions as error code corrected memory regions

Various embodiments of the present invention provide systems and methods for selecting data encoding. As an example, some embodiments of the present invention provide methods that include receiving a data set to be written to a plurality of multi-bit memory cells that are each operable to hold at least two bits. In addition, the methods include determining a characteristic of the data set, and encoding the data set. The level of encoding is selected based at least in part on the characteristic of the data set. In some instances of the aforementioned embodiments, the characteristic of the data set indicates an expected frequency of access of the data set from the plurality of multi-bit memory cells.

Systems and methods for selecting bit per cell density of a memory cell based on data typing

Systems and methods for implementing error correction in relation to a flash memory

Various data acquisition, storage and/or distribution systems and devices are described herein. As one example, a mobile data acquisition and distribution device is described. The device includes a non-volatile storage medium, a wireless interface, and a processor. The non-volatile storage medium includes instructions executable by the processor to: receive a user data set, and to store the user data set to the non-volatile storage medium. The instructions are further executable by the processor to receive a request initiated through a remote user interface via the wireless interface. Where the request is to provide the user data set to a recipient device, the instructions are further executable by the processor to provide the user data set to the recipient device via the wireless interface.

Systems and methods for mobile data storage and acquisition

Various embodiments of the present invention provide for extended life operation of multi-bit memory cells. As an example, some embodiments of the present invention provide electronic systems that include a plurality of multi-bit memory cells, an encoding circuit and a decoding circuit. Each of the plurality of multi-bit memory cells is operable to hold at least two bits. The encoding circuit is operable to receive a data input including at least two data bits, and to encode the two data bits as an encoded output to the plurality of multi-bit memory cells. The encoded output may be selected to be either a single two bit output representing the two bits, or a series of two two bit outputs representing the two bits. The decoding circuit is operable to reverse the encoding applied by the encoding circuit.

Systems and methods for extended life multi-bit memory cells

A power management circuit is provided for a data storage device that is adapted for communicating with a host via an interface circuit. The power management circuit is responsive to a utilization of a control circuit of the data storage device, determined independently of the communication between the data storage device and the host, in providing a supply power to the data storage device. A method is provided comprising connecting a data storage device with a host via an interface circuit; sending data transfer commands from the host to the interface circuit; and monitoring the utilization of a control circuit of the data storage device in terms of the rate at which commands are processed by the control circuit for use in selectively providing a supply power to the data storage device.

Power management in data storage device determining utilization of a control circuit by its rate of command processing

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Loveland, CO, United States of America

Robert Warren