National Semiconductor Corporation

Robert Walter Williams

Robert James Divivier

Mario D Nemirovsky

Roy K Yamanouchi

A computer with a pipelined processor and code breakpoints for performing software debug operations includes prefetch and decode stages, debug address registers for storing code breakpoints representing addresses of preselected instructions, and two digital comparators. During the instruction prefetch phase of operation, the first comparator compares the 29 most significant bits �31:3! of the 32-bit prefetch instruction address against the code breakpoints stored in the debug address registers and produces a 1-bit signal indicating whether such comparison results in a positive match. Subsequently, during the decode phase of operation, the second comparator compares the three least significant bits �2:0! of the 32-bit prefetch instruction address and produces a 1-bit signal indicating whether such comparison results in a positive match. These two 1-bit signals are then logically ANDed, synchronized with bit 3 �2! of the 32-bit prefetch instruction address to ensure that such two 1-bit signals are based upon corresponding comparisons of the same prefetch instruction address.

Code breakpoint decoder

Each cell of a static latch implemented in MOS transistor circuitry includes an MOS transistor configured to operate a depletion mode and operably coupled to communicate an output node of the cell to an input node of the cell in absence of a control signal, to effect the latching operation. Presence of the control signal allows data to be efficiently written to the cell by enabling a transfer gate to establish a communication path for the data to the input node of the cell, while at the same time disabling the MOS transistor to terminate communication of the output node of the cell to its input node during the write operation.

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San Jose, CA, United States of America

Robert Walter Williams