International Business Machines Corporation

Qualcomm Incorporated

Sony Computer Entertainment Inc.

Toshiba America Electronic Components, Inc.

Robert Walter Berry, Jr

Prasanna Jayaraman

Anand Haridass

Tony Emile Sawan

Christopher J Kuruts

Michael Stephen Floyd

Michael Edward Criscolo

James P Kuruts

Ryan Joseph Pennington

Philip George Shephard, Iii

Steven Joseph Smolski

Vijay Anand Mathiyalagan

Michael Timothy Saunders

Gulsun Yasar

Jarom Pena

Diyanesh B Chinnakkonda

Diyanesh Babu Vidyapoornachary Chinnakkonda

Catherine Sherry

Eakambaram Rangaswamy Thirumalai

Sang Hoo Dhong

Charles Ray Johns

Kirk David Peterson

David William Boerstler

William Vincent Huott

Jieming Qi

Eskinder Hailu

Alan J Drake

Jonathan James DeMent

Yosuke Muraki

Joab Daniel Henderson

Makoto Aikawa

John Samuel Liberty

Byron Lee Krauter

Pradip Patel

Stephen Douglas Weitzel

Kazuhiko Miki

Gilles Gervais

Iwao Takiguchi

Tetsuji Tamura

Bernd K Koenemann

Charles Meissner

Kenneth D Wagner

William J Scarpero, Jr

Pedro Martin-de-Nicolas

Divya Kumar

Jacob Savir

Frederick J Cox

Christopher R Conley

Richard L Willaman

Paul R Turgeon

Joseph B Hanley, Iii

It is determined that a guard band frequency for a first processor is to be determined. The guard band frequency is associated with a first system configuration. A validation start frequency is determined based, at least in part, on data associated with at least one of the first processor or a second processor. The validation start frequency is between a nominal operating frequency for the first processor and a system maximum operating frequency for the first processor. A guard band frequency for the second processor was previously determined. The guard band frequency for the first processor is determined based, at least in part, on the validation start frequency.

Frequency guard band validation of processors

An enhanced dual in line memory module (DIMM) connector includes internal conductive paths that provide access to signaling on standard conductive paths to an industry standard DIMM. The internal conductive paths are coupled in series or in parallel with the standard conductive paths through the connector. Interposer circuitry, such as control circuitry and or supplemental memory circuitry, may be incorporated on or within the connector. The interposer circuitry may include field effect transistor (FET) switching circuitry configured to selectively decouple a defective dynamic random memory (DRAM) on a DIMM from a conductive path to a memory controller and couple a substitute DRAM to the conductive paths in its place.

Dual in line memory module (DIMM) connector

A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-&#xe0;-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-&#xe0;-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified.

Detecting cross-talk on processor links

An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided.

Processor noise mitigation using differential crictical path monitoring

An approach is provided in which a cooling manager retrieves pre-characterization data corresponding to a fan that electronic components included in a computer system. The pre-characterization data includes operational zones based upon fan power measurements and fan speed settings. The cooling manager sets the fan to a first speed setting within a first operational zone, and detects that one of the components generates a temperature change value that exceeds a specified temperature change value corresponding to the component. In turn, the cooling manager selects a second operational zone and sets the fan to a second speed setting within the second operational zone.

Thermal control system based on nonlinear zonal fan operation and optimized fan power

Processor noise mitigation using differential critical path monitoring

Guardband validation for a device having a critical path monitor involves first applying multiple calibration settings to the monitor during functional operation of the processor, and recording corresponding guardbands which result in reduced timing margin. A desired guardband can later be selected for validation. The calibration settings can be based on delays for a critical path. A calibration test procedure can be used to determine the calibration delays for different operating frequencies or voltages that are set or, alternatively, the calibration delays can be set and resultant frequencies measured which are used to calculate the guardband amounts. The critical path monitor may include a modified calibration delay circuit which provides a calibrated delay signal to a critical path synthesis circuit, and the multiple calibration settings can be applied by changing delay taps of the calibration delay circuit in response to a bias delay signal from a power management controller.

Characterization and functional test in a processor or system utilizing critical path monitor to dynamically manage operational timing margin

A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.

Characterization and validation of processor links

Whether validation of at least one of a plurality of previously validated processors on a first system produced data usable for computing a validation start frequency of an unvalidated processor on a second system is determined. If validation of at least one of the plurality of previously validated processors on the first system produced data usable for validating the unvalidated processor, a validation start frequency associated with the unvalidated processor can be computed based, at least in part, on system parametric data associated with a subset of the plurality of previously validated processors that were validated on the first system. Otherwise, the validation start frequency associated with the unvalidated processor is computed based, at least in part, on tester parametric data associated with the unvalidated processor. Validation of the guard band frequency for the unvalidated processor is initiated at the validation start frequency.

A method for electronically fused encryption key security includes inserting a plurality of inverters between a bank of security fuses and a fuse sense logic module. The method also includes sensing an activated set of the bank of security fuses and the plurality of inverters. The method further includes comparing the sensed activated set of the bank of security fuses and the plurality of inverters with a software key to determine whether at least a substantial match is made.

Method for security in electronically fused encryption keys

A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.

Implementing a programmable DMA master with write inconsistency determination

A system and method for semiconductor identification chip read out is presented. A user uses a stand-alone handheld device to extract product data, which includes manufacturing process attributes, from a semiconductor device. The semiconductor device couples to the hand held device through a subset of pins, such as a power pin, a ground pin, a clock in pin, and a data out pin. When coupled, the handheld device provides a clock signal to the semiconductor device. In turn, on chip logic within the semiconductor device detects the clock signal and gathers internal product data. Once gathered, the on chip logic provides the product data to the hand held device through the data out pin for a user to view. As a result, the user may track semiconductor devices more efficiently.

System and method for semiconductor identification chip read out

Growing community of inventors

Round Rock, TX, United States of America

Robert Walter Berry, Jr