Intersil Americas Inc.

Harris Corporation

Robert W Webb

Douglas Lawton Youngblood

Gregg D Croft

Roger Levison

A method of adaptively controlling a charge pump including coupling the charge pump to a control node, toggling a clock input between supply voltage levels to charge an a charge pump output, monitoring the charge pump output, maintaining the control node at a supply voltage level when a supply voltage magnitude does not exceed a threshold level, and adjusting the control node to maintain the charge pump output at a limit level when the supply voltage magnitude exceeds the threshold level. A positive charge pump embodiment charges the output to twice the positive supply voltage up to no more than a limit level. A negative charge pump embodiment charges the output to the same magnitude with opposite polarity as the positive supply voltage, and decreases the output magnitude if the positive supply voltage is above the threshold level. A Zener diode and controlled current mirror may be used for control.

Adaptive charge pump

A body control apparatus for an analog switch for minimizing leakage current and keeping PN junctions reverse-biased. The analog switch has first and second switch device clusters coupled between input and output nodes and controlled by a control input, each having a corresponding body junction. The body control apparatus includes body control devices each controlled by one of the input and output nodes for coupling a body junction to the opposite one of the input and output nodes. Each switch device cluster may include a main switch and body devices which keep the body junction of the main switch at a voltage level between the input and output nodes when the analog switch is on. When the analog switch is off, the body control apparatus activates when voltage across the input and output nodes rises to keep the body junctions at desired voltage levels.

Analog switch with internal device body control

A switch circuit including a first switch, a reference device, a current generating device and a comparator. The first switch has a first resistance and develops a first voltage when a first current is provided through it. The reference device has a second resistance which is a known multiple of the first resistance. The current generating device provides a reference current through the reference device which develops a second voltage having a level indicative of a maximum current level of the first current. The comparator compares the first and second voltages and provides a maximum current indication. An amplifier may be used to force one side of the first switch and the reference device to the same voltage, where the reference device is coupled between an input and an output of the amplifier. The switch circuit may include a calibration mode.

Analog switch with overcurrent detection

An integrated analog switch including first and second semiconductor devices and a current mirror. The first device is a switching device having first and second current terminals coupled between first and second switch terminals. When turned off, the body of the first device is pulled to a bias voltage, and a first leakage current flows between its body and the first switch terminal. The second device is a reduced-size replica of the first device having one current terminal coupled to the first switch terminal and having its body pulled to about the bias voltage when turned off. The second device provides a second leakage current which is proportional to the leakage current of the first device. The current mirror circuit mirrors and amplifies the second leakage current to provide a cancellation current which is applied to the first switch terminal to cancel leakage current.

Leakage current cancellation for integrated analog switch

A switch circuit, which selectively couples first and second switch nodes together and which enables the first and second switch nodes to operate in an extended voltage range, includes a secondary voltage rail, a switch device, a body driver, a rail control switch, and a switch control circuit. The rail control switch clamps the secondary voltage rail to a primary voltage rail during normal voltage range operation, but otherwise releases the secondary voltage rail to float. The body driver clamps the body of the switch to the secondary voltage rail when turned on, and when turned off, forward biases to allow voltage of said secondary voltage rail to follow voltage of the switch nodes into the extended voltage range through the switch. The switch control circuit includes a latch circuit which ensures that the switch remains either turned on or turned off during extended voltage operation.

Analog switch for operation outside power rails with low supply current

A current mode (NOR) logic circuit includes a first, fixed reference current source transistor stage coupled in circuit between a first voltage supply terminal and an input current node. A second, variable current source transistor stage is coupled in circuit between the first voltage supply terminal and the input current node. The second, variable current source supplies a variable quantity of auxiliary current to the input current node in dependence upon whether the input node sees a high logical level current or a low logic level current. The magnitude of the auxiliary current is such that the total of the auxiliary current and the prescribed reference current balances the input current being supplied to the input current node. A current switch transistor has its collector-emitter current flow path coupled in circuit between the first current source and one or more output current transistors. Base biasing of the current source transistors and the current switch transistor is independent of the power distribution bus for the overall system architecture in which the NOR gate is employed, so that the operations of the transistor stages are effectively immune to current transients on the power distribution bus. In addition, the bias voltages are such as to prevent transistor stages from operating in a saturation condition for either of the first and second input current levels, so that the speed-power product of the logic circuit is increased.

High speed bipolar digital logic gate architecture

An input circuit for an operational amplifier which incorporates a bias control transistor for effectively minimizing the input current to a Darlington-connected transistor pair into the same semiconductor region in which the Darlington-connected transistor pair is formed. All portions of the surface of the dielectrically isolated island are effectively boot-strapped with the (common mode) input signal, whereby the parasitic capacitance to ground is effectively eliminated. This enables the collector current of the input transistor to be reduced significantly relative to the collector current flowing through the output transistor of the Darlington pair. To accommodate for device characteristic variations among separate wafer processing runs, a self-balanced bias circuit, containing a transistor pair matched to the bias and Darlington output transistors, is employed as the current source of the operational amplifier. As a result, the ratio of the collector currents of the Darlington-connected pair can be controlled irrespective of saturation currents or sheet resistivity of bias resistances employed for the bias control transistor and for the self-balanced bias circuit respectively.

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Palm Bay, FL, United States of America

Robert W Webb