Motorola Corporation

Visa U.s.a. Inc.

Robert W Seaton, Jr

L Rodney Goke

Michael G Gallup

Terry G Lawell

Thomas J Tomazin

Stephen G Osborn

Terence Paul Spielman

Jason Spielman

Yee-Wei Huang

Neal Blackwood

Michael T Clay

Penny Cornwell

Michael G Gallup, Deceased

Micheal G Gallup

A system and method configured to provide secure Personal Identification Number (PIN) based authentication is disclosed. A passcode or PIN associated with a customer value card can be securely authenticated by an issuer prior to authorizing payment. An Access Control Server (ACS) can receive the PIN or passcode from a customer via a secure connection over a public network. The ACS can generate an encrypted PIN and can communicate the encrypted PIN to a remote issuer for authentication. The ACS can use one or more hardware security modules to generate the encrypted PIN. The hardware security modules can be emulated in software or implemented in hardware. The system can be configured such that the PIN is not exposed in an unencrypted form in a communication link or in hardware other than the originating customer terminal.

Method and system for secure authentication

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Data processing system and method thereof

A computer-implemented method is provided for compiling software code that performs nested conditional constructs in vector data processors (10). A vector bit stack (128) to record which processing elements (16) were activated and which processing elements were deactivated during execution of a nested conditional construct. Subsequently, when an end of a first nested conditional construct is encountered, a state of the processing elements at a point in time in which the first nested conditional construct was initiated may be popped off of the vector bit stack and a second conditional construct or any other operation may be executed. Therefore, conditional constructs may be executed while ensuring the proper state of the processing elements. The compiler program effectively utilizes the vector bit stack to store prior states of each of the processing elements of the vector data processor such that the processing elements may be efficiently restored to a correct intermediate value.

Efficient stack utilization for compiling and executing nested if-else

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands. The data processing system (55) includes a plurality of instructions which include and utilize an extension bit during execution. In one embodiment, a plurality of instructions, both arithmetic and non-arithmetic, use extension bits for preliminary and non-preliminary instructions in order to accommodate large data widths.

Instruction in a data processing system utilizing extension bits and

A data processor for storing vector data in multiple locations within the processor using a pointer value and a mask value. In one embodiment, a multi-entry input data register is used to receive input data to be provided to a plurality of processing elements. A pointer value is used to address the multi-entry input data register. A mask value may be used to provide the same data to a plurality of locations within the input data register.

Method and apparatus for storing vector data in multiple non-consecutive

Data processor for performing a comparison instruction using selective

A 'vnmvh' instruction reduces a substantial number of instructions and the temporary use of a register in a software code which executes nested conditional constructs in a vector data processor (10). When the vnmvh instruction is executed, all processing elements in the vector data processor participate in the function regardless of a setting of a status bit (Vt bit) (FIG. 6). During execution of the vnmvh instruction, the least significant bits of vector register specified in an operand are negated and moved into a plurality of history bits (Vh bits) (FIG. 6). The functionality provided by execution of vnmvh instruction allows a user to execute a nested conditional construct efficiently and effectively.

Vector move instruction in a vector data processing system and method

Data processor for conditionally modifying extension bits in response to

Growing community of inventors

Austin, TX, United States of America

Robert W Seaton, Jr