Honeywell Information Systems Inc.

Robert W Norman, Jr

Donald C Boothroyd

Marion G Porter

William A Shelly

John E Wilhite

Howard J Keller

Charles P Ryan

Richard T Flynn

The present invention relates to an apparatus for providing a data available indication while inhibiting the reading of operand data beyond the last word of an operand data string. The data available indication operates to enable additional cycles to be generated for completing the execution of the instruction. The apparatus includes a memory element, which has a plurality of locations, each of the plurality of locations corresponding to a respective location of a memory device where the operand data string is stored. The memory element stores information which indicates when the corresponding location is the last word of the operand data string. A read address register which contains the read address value of the memory device includes an input strobe terminal which receives an enable signal based on the information stored in the memory element, thereby enabling or inhibiting the updating of the read address value in the read address register.

Data available indicator for an exhausted operand string

The present invention relates to the operational control of a digital computer system which includes the digital logic circuitry for temporarily storing results internal to an execution unit. An input unit of the execution, which inputs operand words to the execution logic of the execution unit, includes a first stack for holding operand words received from an external memory unit and a second stack for holding the result words of the execution logic. The input unit also includes a switch element for selecting words stored in the first and second stack which are to be utilized as input operand words to the execution logic in response to at least one control signal.

Wraparound buffer for repetitive decimal numeric operations

The present invention relates to a method within a digital computer system for reading operand data stored in a temporary storage memory in a forward or reverse direction. The method includes loading the temporary storage memory with the first and second operand data strings in a pre-established order such that the subsequent fetching of the operand data words from the temporary storage memory is performed in a sequential order. The loading and fetching steps operate to achieve a desired word order such that the operation between operand data strings can be started while the operand data is being fetched.

Method for decreasing execution time of numeric instructions

The present invention relates to an operational control of a digital computer system for reading operand data stored in a temporary storage memory in a forward or reverse direction. The present invention includes an adder for adding the current read address value to a constant thereby generating a new read address value used to read the operand data on the next cycle. A preselected constant is provided to the adder each cycle, which causes the resultant new read address value to forward or reverse read the operand data.

Apparatus for forward or reverse reading of multiple variable length

The present invention relates to an execution unit of a computing system which executes data manipulation type instructions and arithmetic type instructions on data words having a plurality of decimal character-type data formats. The pipelined execution unit of the present invention includes a first stage element which temporarily stores input data, the input data including operation commands defining said decimal type instructions, and input operand data. A second stage element executes a first predetermined group of the decimal type instructions. A third stage element, operatively coupled to said second stage element, executes a second predetermined group of the decimal type instructions, the second predetermined group including arithmetic type instructions.

Pipelined decimal character execution unit

The present invention relates to an alignment network for aligning data words having a plurality of data word formats. A plurality of shifters are utilized, each shifter utilized to shift the corresponding bit of each character. When the output data word format is different from the input data word format, selected characters in response to a predetermined control signal are temporarily stored so that they may be inputted to the shifters on the next shift cycle in order to achieve the desired shifted character order. An alignment switch then aligns or packs the shifted data from the output of the shifters to the predetermined data format in response to a select control signal.

Apparatus for aligning and packing a first operand into a second operand

The present invention relates to digital logic circuitry for detecting a predetermined character of a data string for operand data stored in a temporary storage memory or while the data is being loaded into the temporary storage memory, wherein the data string length and the starting location of temporary storage memory in which the data string is to be stored is variable. A first comparator element compares a write address pointer to a start address pointer and an adder generates a sign pointer which indicates an address of temporary storage memory of the predetermined character. A second comparator element utilizes the pointers and the resultant outputs of the first comparator and the adder to indicate the end of the data string.

Apparatus for detecting a predetermined character of a data string

The present invention relates to an alignment network for aligning data words having a plurality of data word formats. A plurality of shifters are utilized, each shifter utilized to shift the corresponding bit of each character. The odd bits, or nonsymmetrical bits across the various data formats are processed by a separate shifter. In this manner, no pre or post processing of the data word is required in the overall shifting operation.

Data alignment circuit

A cache unit includes a cache store organized into a number of levels to provide a fast access to instructions and data words. Directory circuits, associated with the cache store, contain address information identifying those instructions and data words stored in the cache store. The cache unit has at least one instruction register for storing address and level signals for specifying the location of the next instruction to be fetched and transferred to the processing unit. Replacement circuits are included which, during normal operation, assign cache locations sequentially for replacing old information with new information. The cache unit further includes detection apparatus for detecting a conflict condition resulting in an improper assignment. The detection apparatus, upon detecting such a condition, advances the relacement circuits forward for assigning the next sequential group of locations or level inhibiting it from making its normal location assignment. It also inhibits the directory circuits from writing the necessary information therein required for making the location assignment and prevents the information which produced the conflict from being written into cache store when received from memory.

Cache unit information replacement apparatus

A data processing system comprises a data processing unit coupled to a cache unit which couples to a main store. The cache unit includes a cache store organized into a plurality of levels, each for storing blocks of information in the form of data and instructions. The cache unit further includes an instruction buffer having first and second sections for storing instructions received from main store. Each instruction buffer section includes a plurality of word storage locations, each location having a number of bit positions. A predetermined bit position of each location is used to indicate when an instruction word has been written into the location. Control apparatus coupled to each of the buffer sections is operative to reset all of the word locations to binary ZEROS when a command requesting an instruction block from main store is ready to be transferred thereto. It is set to a binary ONE state when an instruction word is loaded into the location. Instruction buffer ready circuits included within the control apparatus are conditioned by the states of the predetermined bit positions of the locations to generate output signals to the processing unit enabling the transfer of requested instruction words to the processing unit as soon as they are received from main store.

Instruction buffer apparatus of a cache unit

A cache unit includes a cache store organized into a number of levels to provide a fast access to instructions and data words. Directory circuits, associated with the cache store, contain address information identifying those instructions and data words stored in the cache store. The cache unit has at least one instruction register for storing address and level signals for specifying the location of the next instruction to be fetched and transferred to the processing unit. Replacement circuits are included which, during normal operation, assign cache locations sequentially for replacing old information with new information. The cache unit further includes apparatus operative in response to a first predetermined type of command specifying the fetching of data words to set an indicator flag to a predetermined state. The apparatus conditions the replacement circuits in response to each subsequent predetermined type of command to bypass storage of the subsequently fetched data words when the indicator flag is in the predetermined state preventing the replacement of extensive numbers of data and instruction words already stored in cache during the execution of the instruction.

Cache unit bypass apparatus

A cache system includes a high speed storage unit organized into a plurality of levels, each including a number of multiword blocks and at least one multiposition address selection switch and address register. The address switch is connected to receive address signals from a plurality of address sources. The system further includes a directory organized into a plurality of levels for storing address information required for accessing blocks from the cache storage unit and timing circuits for defining first and second halves of a cache cycle of operation. Control circuits coupled to the timing circuits generate control signals for controlling the operation of the address selection switch. During the previous cycle, the control circuits condition the address selector switch to select an address which is loaded into the address register during the previous half cycle. This enables either the accessing of instructions from cache or the writing of data into cache during the first half of the next cache cycle. During the first half of the cycle, the address selected by the address switch in response to control signals from the control circuits is clocked into the address register. This permits processor operations, such as the accessing of operand data or the writing of data into cache to be performed during the second half of the same cycle.

Cache arrangement utilizing a split cycle mode of operation

A cache system includes a storage unit organized into a plurality of levels, each including a number of multiword blocks and a corresponding number of address selection switches and address registers. Each address selection switch has a plurality of different positions connected to receive address signals from a plurality of address sources. A decoder circuit generates output signals for controlling the operation of the address selection switches. In response to previously defined level signals, the decoder circuit conditions a specified one of the number of switches to switch from a first position to a second position. An address specifying the location into which memory data is to be written is clocked into one address register while the address specifying the location from which an instruction is to be fetched is clocked into the remaining address registers. A comparator circuit compares signals indicating the level into which memory data is to be written with signals indicating the level from which a next instruction is to be fetched. The comparator circuit generates signals which cause the delay of instruction access when there is a conflict between writing memory data and accessing instructions.

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Glendale, AZ, United States of America

Robert W Norman, Jr