Dallas Semiconductor Corporation

Texas Instruments Corporation

Robert W Mounger

Robert D Lee

William Richard Ezell

Titkwan Hui

George Vincent Konnail

John P Heptig

Richard E Downs

Jose Vicente Santos

Sanjay Pratap Singh

In a method and apparatus for saving power in a device coupled to a bus, the device is placed to operate in a power saving mode by powering off a selective portion of the device including a device clock. If data communication over the bus is addressed to the device then the selective portion of the device, including the device clock, is triggered to return to a power on state from the power off state. The data communication is stored in shadow registers using a bus clock while the device clock is transitioning to the power on state. The data communication stored in the shadow registers is transferred to a register map under the control of the device clock operating in the power on state. Upon completion of the transfer of the data communication to the register map, the device is returned to operate in the power saving mode.

Power efficient method for controlling an oscillator in a low power synchronous system with an asynchronous I2C bus

A circuit and associated method for determining the offset bias of a comparator by first shorting together the inputs of the comparator to apply the same voltage signal at each of the inputs of the comparator. The voltage signal at one of the inputs is then offset a select amount by applying varying selected resistances from a variable resistor to the comparator. The variable resistor is controlled by a programmable controller that is responsive to an input clock signal. At each selected amount of offset applied to the input, the output is monitored to determine if the output of the comparator has flipped, or changed state. When the output flips, the corresponding resistance setting is used to compensate for the corresponding offset bias of the comparator.

Auto zero circuitry and associated method

Digital signal delay lines with electrically programmable and trimmable delay times, including electrically erasable and reprogrammable delay times. Floating gate field effect transistors are programmed to select current, capacitance, and/or threshold and thereby set a delay time determined by acurrent charging of a capacitor up to a threshold voltage. Trimming after packaging avoids package offsets. Temperature and power supply voltage compensation by current combining gives compensation compatible with the electrical programming.

Programmable delay line

An electronic device for monitoring the operating conditions of a rechargeable battery, and includes a temperature monitor for monitoring the operating temperature of the rechargeable battery; a voltage determiner coupled to the rechargeable battery for measuring the potential level of the rechargeable battery; a one wire interface for outputting the information corresponding to the potential level of the rechargeable battery and the information corresponding to the temperature monitored by the temperature monitor; and a power regulator coupled to the rechargeable battery for supplying regulated power from the rechargeable battery to the temperature monitor and the voltage determiner. The voltage determiner includes an analog to digital converter and utilizes a successive approximation technique to determine and output a digital value corresponding to the potential level of the rechargeable battery.

Battery pack monitoring system

The present invention regulates a power signal provided by a power source and includes two operational modes: a first mode capable of consuming low amounts of static power; and a second mode capable of smoothing voltage spikes appearing at high frequencies. The present invention further includes a generator, amplifier, and a regulator for controlling the power signal; a device for determining whether the present invention should be in the first or second operational mode; and a device for shifting between the first and second operational modes.

Digitally adaptive biasing regulator

Programmable delay lines

An integrated circuit filter wherein two digital inverters are used, with cutoff frequencies which bracket the desired passband frequency. (The cutoff frequency of the two digital inverters is selected by changing their RC time constants.) The inverter with the lower cutoff frequency has its output connected to the reset input of a counter, and the inverter with the higher cutoff-frequency has its output connected to the clock input of a counter.

Differential-time-constant bandpass filter using the analog properties

An integrated circuit which uses an unusual comparator design, which is not fully complementary but which has an extended common mode range, to control switching of one pole of the output driver (e.g. the lower pole) between an internal voltage (e.g. ground voltage) and a current extracted from an incoming signal.

Sensitive low power comparator

An integrated circuit filter wherein two digital inverters are used, with cutoff frequencies which bracket the desired passband frequency. (The cutoff frequency of the two digital inverters is selected by changing their RC time constants.) The inverter with the lower cutoff frequency has its output connected to the reset input of a counter, and the inverter with the higher cutoff frequency has its output connected to the clock input of a counter.

A RF receiver with extremely low standby power consumption. To minimize power consumption during standby, the analog input from the antenna circuit (including tank resonator) is connected directly to the inputs of a comparator. Preferably two comparators are used, each connected to a separate antenna. Thus, a signal loss due to antenna nulls will be minimized. Preferably a following stage decodes a pulse-width-modulated (or burst-length-modulated) signal. If the length of pulses substantially exceeds the expected maximum, the following stage provides a control signal to reduce the gain of the input comparators.

Low-power RF receiver

A micropowered module containing an integrated circuit packaged with a battery. The module is originally in a state of zero power consumption. When the module is to be put into use, a very strong electromagnetic field is applied at a predetermined frequency. A preset pulse code at this frequency will activate logic elements to keep the integrated circuit turned on, in active or standby mode. In standby mode, the power from the battery will avoid data loss.

Growing community of inventors

Dallas, TX, United States of America

Robert W Mounger