Eaton Corporation

Cutler-hammer, Inc.

Robert W Lade

Herman P Schutten

James A Benjamin

Stanley V Jaskolski

Gordon B Spellman

Joseph Charles Zuercher

Erlen B Walton

James R Jaeschke

Roy Hyink

Michael J Schutten

Stanley V Jasolski

Lawrence E Van Horn

The depth of a cavity or chamber (10') is measured by using the chamber as the resonator of an electronic oscillator (24) whose oscillations are coupled to fluid in the cavity by transducers (12, 13). Both the variable-depth main chamber (10') and a reference chamber (117) of fixed depth are measured. Variations in the data obtained from the chambers are caused by factors affecting the velocity of propagation of sound in the fluid. An accurate measurement of the depth of the main chamber is obtained by compensating direct data (at 42) obtained from the main chamber (10'), using, data (at 43) obtained from the fixed-depth reference chamber (117). In one embodiment an inertance orifice (121) is utilized between the two chambers. The fluid inertance of the orifice, together with the compliance of the fluid in the main chamber (10'), form a resonant system whose anti-resonant frequency is a measure of the dimensions of the main chamber. (Inertance is the acoustical equivalent of inductance.)

Apparatus for measuring depth of a fluid chamber

A cavity such as a chamber (10) of a hydraulic cylinder (2) containing a movable piston (4) is equipped with transducers (12) for transmitting alternating pressure signals into a fluid in the chamber and for receiving signals from it. The fluid chamber acts as a resonant tank circuit for determining the frequency of an external electronic oscillator (24). The frequency of oscillation of the circuit indicates the depth of the cavity, i.e., the position of the piston in the cylinder. Multiple modes of oscillation are employed (34, 36) in the same chamber to provide high accuracy and resolution of ambiguities. In one embodiment chambers (10', 66) on both sides of the piston (4') of a double-acting cylinder (2') are measured, and the readings are combined (76) to reduce errors that would otherwise result from changes in temperature, pressure, viscosity and other parameters unrelated to the position of the piston.

Cylinders having piston position measurement

MOMOM structural geometry and fabrication techniques are disclosed. A first oxidizable metal strip (3) and a second coplanar nonoxidizable metal strip (6) are deposited on an insulating substrate (2). An insulating layer (12) is deposited on the metal strips, followed by deposition of a third nonoxidizable metal layer. A generally vertical notch (14) is cut through the layers to the substrate providing left and right sections (15, 16) of the third metal layer, left and right sections (19, 20) of the insulating layer, and the first and second metal layers with facing edges (23, 24) spaced by the notch therebetween. An oxidized tip (25) is formed at the facing edge of the first metal layer. A fourth metal layer (26) is ballistically deposited over the oxidized tip and the left section of the third metal layer, using the notch edge of the right section of the third metal layer as a shadow mask, followed by oxidization of the fourth metal layer. A fifth horizontal metal layer (30) is ballistically deposited by a vertically columnated beam along the substrate across the bottom (28) of the notch between the oxidation layer on the fourth metal layer and the facing edge (24) of the second metal layer. The M-O-M-O-M structure is provided by the first metal layer (3)--the oxidized tip (25)--the fourth metal layer (26) at a generally vertical portion (39)--the oxidation layer (29) on the fourth metal layer at a generally vertical portion (41)--the fifth metal layer (30) and the second metal layer (6).

Method for making horizontally layered momom tunnel device

MOMOM structural geometry and fabrication techniques are is disclosed. First and second metal layer strips (6 and 10) are supported on an insulating substrate (4) and have vertically overlapped portions sandwiched between insulating layers (8, 12). A generally vertical side (18) is defined through the layers to the substrate to expose vertical edges (20, 24) of the metal layers which are oxidized (32, 34) and covered by a third metal layer (44) extending therebetween. In the preferred embodiment, the middle insulating layer (8) is undercut (28), oxidized (36, 40), and filled with metallization (50), to provide a vertical rectilinear conduction path.

Method for making vertically layered MOMOM tunnel device

A power JFET (2) has a stack (4) of alternating conductivity type layers (5-9) forming a plurality of channels (6, 8). The JFET has an ON state conducting bidirectional current horizontally through the channels. The channels are stacked vertically, and the JFET has an OFF state blocking current flow through the channels due to vertical depletion pinch-off. Various main and gate terminal and drift region structures are disclosed.

Multi-channel power JFET with buried field shaping regions

MOMOM structural geometry and fabrication techniques are disclosed. First and second metal layer strips (6 and 10) are supported on an insulating substrate (4) and have vertically overlapped portions sandwiched between insulating layers (8, 12). A generally vertical side (18) is defined through the layers to the substrate to expose vertical edges (20, 24) of the metal layers which are oxidized (32, 34) and covered by a third metal layer (44) extending therebetween. In the preferred embodiment, the middle insulating layer (8) is undercut (28), oxidized (36, 40), and filled with metallization (50), to provide a vertical rectilinear conduction path.

Vertically layered MOMOM tunnel device

A power JFET (2) has a common drift region (4) between split first and second longitudinally separated sets of rows (6, 8) of alternating conductivity type layers (10-20 and 21-31) forming a plurality of channels (11, 13, 15, 17, 19, 22, 24, 26, 28 and 30). The JFET has an ON state conducting bidirectional current horizontally longitudinally through the common drift region and the channels. The JFET has an OFF state blocking current flow through the channels due to horizontally lateral depletion pinch-off. The layers of the rows extend vertically and horizontally longitudinally such that the direction of layering extends horizontally laterally. Particular gate structure is disclosed.

Split row power JFET

A power JFET (2) has a common drift region (4) between a pair of spaced first and second stacks (6, 8) of alternating conductivity type layers (10-14 and 15-19) forming a plurality of channels (11, 13, 16 and 18). The JFET has an ON state conducting bidirectional current horizontally through the common drift region and the channels. The channels are stacked vertically, and the JFET has an OFF state blocking current flow through the channels due to vertical depletion pinch-off. Field shaping and high blocking voltage capability are provided. Particular main terminal and gate structure is disclosed.

Dual stack power JFET with buried field shaping depletion regions

MOMOM structural geometry and fabrication techniques are disclosed. A first oxidizable metal strip (3) and a second coplanar nonoxidizable metal strip (6) are deposited on an insulating substrate (2). An insulating layer (12) is deposited on the metal strips, followed by deposition of a third nonoxidizable metal layer. A generally vertical notch (14) is cut through the layers to the substrate providing left and right sections (15, 16) of the third metal layer, left and right sections (19, 20) of the insulating layer, and the first and second metal layers with facing edges (23, 24) spaced by the notch therebetween. An oxidized tip (25) is formed at the facing edge of the first metal layer. A fourth metal layer (26) is ballistically deposited over the oxidized tip and the left section of the third metal layer, using the notch edge of the right section of the third metal layer as a shadow mask, followed by oxidization of the fourth metal layer. A fifth horizontal metal layer (30) is ballistically deposited by a vertically columnated beam along the substrate across the bottom (28) of the notch between the oxidation layer on the fourth metal layer and the facing edge (24) of the second metal layer. The M-O-M-O-M structure is provided by the first metal layer (3)-the oxidized tip (25)-the fourth metal layer (26) at a generally vertical portion (39)-the oxidation layer (29) on the fourth metal layer at a generally vertical portion (41)-the fifth metal layer (30) and the second metal layer (6).

Horizontally layered MOMOM notch tunnel device

A solid display is provided by a semiconductor switched between transparent and opaque conditions according to external removal of carriers from the conduction band for controlling absorption of light-energy. A semiconductor has an energy band gap affording a normally saturated conduction band in response to impinging light energy of a given range wavelength. The normally saturated condition of the semiconductor prevents further absorption, and enables light to pass thererthrough. The semiconductor is switched to an opaque condition by completing an electric circuit for removing carriers from the conduction band to enable further absorption of incident light in the semiconductor by raising additional carriers from the valence band to the conduction band.

Solid state display

A lateral bidirectional power FET (2) has a common drift region (6) between first and second stacks (8, 10) of alternating conductivity type layers (12-17 and 18-23). A notch (38) extends vertically downwardly into the drift region and laterally separates the stacks above the drift region. The stacks include a plurality of channel-containing regions (12-14 and 18-20) interleaved with a plurality of source regions (15-17 and 21-23). In the ON state, bidirectional current flows serially through the source regions and channels of each stack and through the drift region. In the OFF state, voltage is dropped across the plurality of junctions in series in the stacks, and the respective junctions with the drift region.

Lateral bidirectional power FET with notched multi-channel stacking and

Lateral planar FET structure (2) is disclosed for bidirection power switching, including AC application. Voltage blocking capability is enhanced in the lateral current flow device (2) by field shaping in the drift region (22). In the OFF state, the field shaping region (24) straightens field lines and prevents gradient induced depletion and unwanted inversion of conductivity type along a lateral drift region portion (54) extending beneath a top major surface (28) of the substrate between channel-containing regions (6) and (8).

Planar field-shaped bidirectional power FET

Lateral FET structure is disclosed for bidirectional power switching, including AC application. A notch extends downwardly from a top major surface to separate left and right source regions and left and right channel regions, and direct the drift region current path between the channels around the bottom of the notch. Split gate electrodes in the notch proximate the channels control bidirectional conduction, and are at non-common potentials in the OFF state to increase breakdown voltage. Self-shielding of the gates is also disclosed to further increase OFF state breakdown voltage.

Lateral bidirectional notch FET with gates at non-common potentials

An AC solar cell is provided by a pair of PN junction type solar cells connected in antiparallel between a pair of main terminals, and means for directing light alternatingly on the PN junctions to generate an alternating potential across the main terminals. AC electrical energy is generated without a DC to AC converter.

AC Solar cell

Lateral FET structure is disclosed for bidirectional power switching, including AC application. Integral avalanche protection is provided by a pair of isolation regions forming protective barrier junctions with a common layer, which junctions are in parallel with the reverse blocking junctions of the power FET in the OFF state and have a lower reverse breakover threshold for protecting the latter. A plurality of integrated FETs each have left and right source regions and left and right channel regions with a common drift region therebetween, and conduct current in either direction according to the polarity of main terminals.

Growing community of inventors

Fort Myers, FL, United States of America

Robert W Lade