Motorola Corporation

Kla-tencor Technologies Corporation

Kla Tencor Corporation

Robert W Fiordalice

Papu D Maniar

Faivel S Pintchovski

Ramnath Venkatraman

Hisao Kawasaki

T P Ong

Johnson O Olowolafe

Mehdi Vaez-Iravani

Rama I Hegde

Stanley Michael Filipiak

Bernard J Roman

Dean J Denning

Sam S Garcia

Andrew Zeng

Jeffrey L Klein

Jeffrey Alan Rzepiela

Elizabeth J Weitzman

Carl Treadwell

Sergey D Lopatin

Avgerinos V Gelatos

Igor C Ivanov

Artur Kolics

Matthew Thomas Herrick

Cindy Reidsema Simpson

Ajay Jain

Kevin G Kemp

Cristiano Capasso

Lei Zhong

Wen Zhong Kong

Iraj Eric Shahvandi

Leroy Grant

Gregor Braeckelmann

Roc Blumenthal

Dave Kolar

John Fretwell

Kara Lee Sherman

One embodiment relates to a method for detecting defects in circuitry formed on a semiconductor substrate. A first scan of said circuitry is performed by scanning a primary electron beam in a first scan direction relative to said circuitry, and secondary electrons emitted during the first scan are detected so as to form a first voltage-contrast image. A second scan of said circuitry is performed by scanning the primary electron beam in a second scan direction relative to said circuitry, and secondary electrons emitted during the second scan are detected so as to form a second voltage-contrast image. The second scan direction is non-parallel to the first scan direction. The first and second voltage-contrast images are then compared to detect electrically-active defects. Other embodiments, aspects and features are also disclosed.

Detection of defects using transient contrast

A method of forming an electrically conductive via. A first electrically conductive layer is formed, and a second layer is formed on the first layer. The second layer has desired barrier layer properties. A third non electrically conductive layer is formed on the second layer. A via hole is etched through the third layer, thereby exposing a portion of the second layer at the bottom of the via hole. The exposed portion of the second layer at the bottom of the via hole is redistributed so that at least a portion of the second layer is removed from the bottom of the via hole and deposited on lower portions of the sidewalls of the via hole. A fourth electrically conductive layer is formed within the via hole to form the electrically conductive via.

Barrier material formation in integrated circuit structures

An integrated circuit and a method of manufacturing an integrated circuit is provided including providing an integrated circuit having a trench and via provided in a dielectric layer. A nano-electrode-array is formed over the dielectric layer in the trench and via, and a conductor is deposited over the nano-electrode-array. The conductor and the nano-electrode-array are coplanar with a surface of the dielectric layer.

Nano-electrode-array for integrated circuit interconnects

Barrier enhancement

Scattered radiation from a sample surface is collected by means of a collector that collects radiation substantially symmetrically about a line normal to the surface. The collected radiation is directed to channels at different azimuthal angles so that information related to relative azimuthal positions of the collected scattered radiation about the line is preserved. The collected radiation is converted into respective signals representative of radiation scattered at different azimuthal angles about the line. The presence and/or characteristics of anomalies are determined from the signals. Alternatively, the radiation collected by the collector may be filtered by means of a spatial filter having an annular gap of an angle related to the angular separation of expected pattern scattering. Signals obtained from the narrow and wide collection channels may be compared to distinguish between micro-scratches and particles. Forward scattered radiation may be collected from other radiation and compared to distinguish between micro-scratches and particles. Intensity of scattering is measured when the surface is illuminated sequentially by S- and P-polarized radiation and compared to distinguish between micro-scratches and particles. Representative films may be measured using profilometers or scanning probe microscopes to determine their roughness and by the above-described instruments to determine haze in order to build a database. Surface roughness of unknown films may then be determined by measuring haze values and from the database.

Defect detection system

An interconnect (,) is formed overlying a substrate (,). In one embodiment, an adhesion/barrier layer (,), a copper-alloy seed layer (,), and a copper film (,) are deposited overlying the substrate (,), and the substrate (,) is annealed. In an alternate embodiment, a copper film is deposited over the substrate, and the copper film is annealed. In yet another embodiment, an adhesion/barrier layer (,), a seed layer (,), a conductive film (,), and a copper-alloy capping film (,) are deposited over the substrate (,) to form an interconnect (,). The deposition and annealing steps can be performed on a common processing platform.

Method for forming a semiconductor device

The present invention includes a process for forming an intermetallic layer and a device formed by the process. The process includes a reaction step where a metal-containing layer reacts with a metal-containing gas, wherein the metals of the layer and gas are different. In one embodiment of the present invention, titanium aluminide may be formed on the sides of an interconnect. The process may be performed in a variety of equipment, such as a furnace, a rapid thermal processor, a plasma etcher, and a sputter deposition machine. The reaction to form the intermetallic layer is typically performed while the substrate is at a temperature no more than 700 degrees Celsius.

Semiconductor device having a titanium-aluminum compound

A method for insitu performing a cleaning operation along with a physical sputtering operation begins by placing a wafer (,) into a chamber (,). A plasma (,) is generated within the chamber (,) using an inert, noble, or reducing gas. The gas is ionized to form ions (,) within the plasma (,). Power is provided to various components (,and,) within the chamber (,) to ensure that the ions (,) are accelerated towards the wafer (,) during first stages of wafer processing. This acceleration of the ions (,) towards the wafer (,) will clean a surface of the wafer (,). Following this cleaning operation, power supplied within the chamber (,) is altered to accelerate the ions (,) into a reverse direction so that the ions (,) impact a sputter target (,). Due to ionic bombardment of the target (,), a material is sputtered onto a clean surface of the wafer (,) in an insitu manner.

Inert plasma gas surface cleaning process performed insitu with physical vapor deposition (PVD) of a layer of material

A process for fabrication of a multilevel interconnect structure includes the formation of an inlaid interconnect (42) overlying an aluminum layer (34). The inlaid interconnect (42) is formed within an interlevel dielectric layer that is processed to contain an interconnect channel (24) and a via opening (14) residing at the bottom of the interconnect channel (24). The aluminum layer (34) is selectively deposited to fill the via opening (14) at the bottom of an interconnect channel (24). Selective deposition is enhanced by the use of a nucleation layer (20) which is formed on the bottom of the via opening, without being formed on the sidewalls, by use of directional deposition technique such as inductively coupled plasma (ICP) deposition. Nucleation layer (20) eases requirements of a cleaning operation prior to selective deposition and provides a surface from which void-free selective growth can occur.

Process for fabricating a multilevel interconnect

An interconnect structure (10) is formed by filling a dual damascene structure (12) with conductive material. A barrier layer (13) is formed to serve as a seed layer and to prevent the out diffusion of copper. A first conductive layer (14) is formed to fill a first portion (21) of the damascene structure (12). A second conductive layer (16) is then formed to complete the filling of a second portion (22) of the damascene structure. A polishing process is then used to remove any excess material.

Method of forming an interconnect structure

A method of decreasing resistivity in an electrically conductive layer (23) includes providing a substrate (14), using a high density plasma sputtering technique to deposit the electrically conductive layer (23) over the substrate (14), and exposing the electrically conductive layer (23) to an anneal in an ambient comprised of a plasma (21).

Method of decreasing resistivity in an electrically conductive layer

A process for fabrication of a metallized interconnect structure includes the formation of an inlaid interconnect (42) overlying an aluminum layer (34). The inlaid interconnect (42) is formed within an interlevel dielectric layer that is processed to contain an interconnect channel (24) and a via opening (14) residing at the bottom of the interconnect channel (24). The aluminum layer (34) is selectively deposited to at least partially fill the via opening (14) at the bottom of an interconnect channel (24). An adhesion layer (36) is deposited to overlie the aluminum layer (34) within the via opening (14), and a second aluminum layer (38) is blanket deposited and planarized to form the inlaid interconnect (42) in the interconnect channel (24).

Process for fabricating a metallized interconnect

A trench isolation region (32) is fabricated to include a trench liner (28) comprised of aluminum nitride. The aluminum nitride trench liner is useful in borderless contact applications wherein a contact opening (56) is etched in an interlayer dielectric (54) and overlies both an active region. (e.g. doped region 52) and the trench isolation region. During formation of opening using etch chemistry which is selective to aluminum nitride, the trench liner protects a P-N junction at a corner region (58) of the trench to prevent exposing the junction. By protecting the junction, subsequent formation of a conductive plug (60) will not electrically short circuit the junction, and will keep diode leakage to within acceptable levels.

Method for providing trench isolation

A trench isolation region (32) is fabricated to include a trench liner (28) comprised of aluminum nitride. The aluminum nitride trench liner is useful in borderless contact applications wherein a contact opening (56) is etched in an interlayer dielectric (54) and overlies both an active region (e.g. doped region 52) and the trench isolation region. During formation of opening using etch chemistry which is selective to aluminum nitride, the trench liner protects a P-N junction at a corner region (58) of the trench to prevent exposing the junction. By protecting the junction, subsequent formation of a conductive plug (60) will not electrically short circuit the junction, and will keep diode leakage to within acceptable levels.

Method for providing trench isolation and borderless contact

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Austin, TX, United States of America

Robert W Fiordalice