Intel Corporation

Robert W Faber

David A Lee

Gary L Graunke

Brendan Traw

Rajesh Sundaram

Sanjeev N Trika

Richard L Coulson

Shekoufeh Qawami

Robert J Royer, Jr

Rick Coulson

Ningde Xie

David Zimmerman

Jonathan C Lueker

John I Garney

Prashant S Damle

Jeanna N Matthews

Sowmiya Jayachandran

David Wyatt

Jawad Basit Khan

Kiran Pangal

Raj K Ramanujan

Richard Paul Mangold

Brent D Chartrand

Matthew Goldman

Mark Isenberger

Jason A Gayman

Andrew D Bodley

Brendan S Traw

Provided is a non-volatile memory device comprising a plurality of memory cells and memory control logic that when executed performs operations comprising initiating a refresh operation; in response to the refresh operation, performing a read of the memory cells to read values of the memory cells; determining whether the read memory cells have a first value or a second value; and for the memory cells determined to have the first value, rewriting the determined first value to the memory cell, wherein the rewriting operation is not performed with respect to memory cells determined to have the second value.

Refresh logic to refresh only memory cells having a first value

A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

Interface for storage device access over memory bus

A first set representing a first plurality of physical block addresses of a non-volatile memory and a second set representing a second plurality of physical block addresses of the non-volatile memory may be identified. In response to a request to perform a wear leveling operation, first data from a first physical block address of the first set may be swapped with second data from a first physical block address of the second set. A second physical block address of the first set that is adjacent to the first physical block address of the first set may be identified. Third data from the second physical block address of the first set may be swapped with fourth data from a second physical block address of the second set that is adjacent to the first physical block of the second set.

Wear leveling based on a swapping operation between sets of physical block addresses of a non-volatile memory

Examples are given for techniques for entry to a lower power state for a memory device or die. The examples to include delaying transitions of the memory device or die from a first higher consuming power state to a second relatively lower power state using one or more programmable counters maintained at or with the memory device.

Techniques for entry to a lower power state for a memory device

A method is described that entails receiving an address for a read or write transaction to a non volatile system memory device. The method further involves determining a usage statistic of the memory device for a set of addresses of which the address is a member. The method further involves determining a characteristic of a signal to be applied to the memory device for the read or write transaction based on the usage statistic. The method further involves generating a signal having the characteristic to perform the read or write transaction.

Generation of far memory access signals based on usage statistic tracking

Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems and methods allow physical addresses of memory cells subjected to a high number of write cycles to be swapped with physical addresses of memory cells subjected to a lower number of write cycles. The physical address of a group of memory cells is a 'hot address' if the write cycle count for that memory cell group exceeds a specified threshold. If the write cycle count for a group of memory cells does not exceed the specified threshold, then the physical address of that memory cell group is a 'cold address'. The systems and methods allow the specified threshold of write cycle counts to be dynamically incremented to assure that cold addresses are available for swapping with hot addresses in the memory cell address space.

Flexible wear management for non-volatile memory

Embodiments including systems, methods, and apparatuses associated with refreshing memory cells are disclosed herein. In embodiments, a memory controller may be configured to perform a read operation on one or more memory cells in a cross-point non-volatile memory such as a phase change memory (PCM). The one or more memory cells may have voltage values respectively set to a first threshold voltage or a second threshold voltage. Based on the read, the memory controller may identify the memory cells in the cross-point non-volatile memory that are set to the second threshold voltage, and refresh the voltage values of those cells without altering the voltage values of the memory cells in the cross-point non-volatile memory that are set to the first threshold voltage. Other embodiments may be described or claimed.

Refresh of data stored in a cross-point non-volatile memory

An apparatus is described having invert determination logic circuitry to determine if a read data path that transports data read from a PCMS memory device is to be inverted or not inverted as a function of whether information represented by the data was last written in an inverted or non inverted logical state to the PCMS memory device during a refresh of said PCMS memory device.

Efficient PCMS refresh mechanism

Embodiments describe methods, apparatus, and system configurations for providing targeted wear management in nonvolatile memory. Specifically, embodiments may include a memory controller to receive a memory access request directed to a storage unit of the nonvolatile memory. The memory controller may access metadata in the storage unit and determine whether to perform a memory access in accordance with the memory access request based on the state information. Other embodiments may be described or claimed.

Nonvolatile memory wear management

A method and system to facilitate paging of one or more segments of a logical-to-physical (LTP) address mapping structure, such as a table, to a non-volatile memory, such as a NAND flash memory. The LTP address mapping structure is part of an indirection system map associated with the non-volatile memory. By allowing one or more segments of the LTP address mapping structure to be paged to the non-volatile memory, the amount of volatile memory required to store the LTP address mapping structure is reduced while maintaining the benefits of the LTP address mapping structure. One or more segments of the logical to physical address mapping structure may be cached in volatile memory, and a size of each segment may be the same as or a multiple of a page size of the NAND flash memory. A lookup or segment table may be provided to indicate a location of each segment and may be optimized for sequential physical addresses.

Method and system for managing a NAND flash memory by paging segments of a logical to physical address map to a non-volatile memory

Embodiments of the invention describe methods, systems and apparatuses to improve solid state device (SSD) write speed by efficiently utilizing error correction code executed for the device. SSDs may be comprised of several NAND memory devices. It is understood that such devices tend to have a raw bit error rate (RBER) that is related to the program/erase cycle count for the device. Embodiments of the invention efficiently use system ECC by changing the operating conditions of the SSD to better utilize the robustness of the implemented ECC algorithm. For example, embodiments of the invention may alter the programming voltage supplied to an SSD to increase write speed; such an increase may increase the RBER of the device, but will not affect the accuracy of such operations due to the ECC that is provisioned for end of life storage fidelity (i.e., the RBER that will occur at the end of life).

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Hillsboro, OR, United States of America

Robert W Faber