Sandisk Technologies Inc.

Smart Storage Systems, Inc.

Western Digital Technologies, Inc.

Sandisk Enterprise IP LLC

Adtron Corporation

Smart Modular Technologies (az) , Inc.

Robert W Ellis

James M Higgins

Gregg Steven Lucas

Mark Joseph Dancho

David Lee Dean

Kenneth B Delpapa

Kevin M O'Toole

James Fitzpatrick

Ryan R Jones

Kevin L Kilzer

Todd Lindberg

Jacob Schmier

Bernardo Rub

Rudolph J Sterbenz

Vidyabhushan Mohan

Lace J Herman

Aaron Keith Olbrich

Jack Frayer

Vivek Shivhare

Atif Hussain

Steven Theodore Sprouse

Stephen Gold

Navneeth Kankani

Neil Richard Darragh

Daniel P Fogelson

Scott Creasman

Alan A Fitzgerald

Venugopal Garuda

Dennis Bennett

David A Wright

Kenneth B DelPapa

Chang Hua Siau

Daniel Lee Helmick

Grishma Shah

Joseph Curtis Taylor

Brent William Jacobs

Gopinath Balakrishnan

Alexander Kwok-Tung Mak

Scott E Harrow

Richard S Lucky

Michelle Martin

Sheunghee Park

Bobby Ray Southerland

Robert V Lazaravich

Hugh Littlebury

Theron Wayne Virgin

John Scaramuzzo

Neil R Darragh

David Dean

Aspects of a storage device are provided that simplify the encoding or translation of optimized read voltage thresholds into a given NAND register format, which may vary depending on NAND technology, block type, page type, or gray code layout. The storage device may include a memory, a circuit that is configured to shift and combine read threshold voltage offsets into a joint read voltage threshold offset, and a controller configured to store the joint read voltage threshold offset in the memory. The circuit may be implemented in hardware of the controller. Alternatively, the controller software or firmware itself may shift and combine the read threshold voltage offsets into the joint read voltage threshold offset. As a result, the number of instructions that the controller typically performs in translating the optimized thresholds may be reduced. Moreover, the simplified translation may be scalable to different NAND technologies or page types.

Optimized threshold translation from serialized pipeline

Aspects of a storage device including a master chip controller and a slave chip processor and memory including a plurality of memory locations are provided which allow for simplified processing of descriptors associated with host commands in the slave chip based on an adaptive context metadata message from the master chip. When the controller receives a host command, the controller in the master chip provides to the processor in the slave chip a descriptor associated with a host command, an instruction to store the descriptor in the one of the memory locations, and the adaptive context metadata message mapping a type of the descriptor to the one of the memory locations. The processor may then process the descriptor stored in the one of the memory locations based on the message, for example, by refraining from identifying certain information indicated in the descriptor. Reduced latency in command execution may thereby result.

Adaptive context metadata message for optimized two-chip performance

Aspects of a storage device including a memory and a controller are provided which allow for detection of dropped commands based on a die status (ready/busy status) of a command received from a host device. The memory may include dies controlled by chip-enables (CE). After selecting a die using CE, the controller waits between a minimum and maximum time after receiving the command to query the die status, where the minimum time is the time by which the command is expected to begin execution and the maximum time is the shortest time by which the command is expected to complete execution. The controller queries the die status after waiting the time period. If the die status is ready when it should have read busy, the controller detects that the command associated with the data is dropped and requests the host device to reissue the command.

NAND dropped command detection and recovery

Aspects of a storage device including a memory and an encryption core are provided. The storage device may be configured for providing secure data storage, as well as one or more post-processing operations to be performed with the data. The encryption core, which may be configured to decrypt data, may control execution of one or more post-processing operations using the data. A read command received from a host device may include a tag associated with data identified by the read command. When encrypted data is retrieved from memory according to the read command, the encryption core may decrypt the encrypted data and provide the decrypted data for post-processing based on the tag. A corresponding post-processing operation may return a result when executed using the decrypted data. Rather than raw data identified by the read command, the result may be delivered to the host device in response to the read command.

Just-in-time post-processing computation capabilities for encrypted data

Aspects of a storage device including a memory and a controller are provided that allow for storage of tags identifying data types and sequence numbers with data to facilitate data recovery and system integrity checks following a power failure or other system failure event. The controller is configured during a write operation to include a tag in the data identifying the data type as a host write, a recycle write, or another internal write. Following a system failure event, the controller is configured to read the tags to identify the data type in the write. Based on the tags, the controller is configured to properly rebuild or update a logical-to-physical (L2P) table of the storage device to assign correct logical addresses to the most recent data during data recovery, as well as to verify correct logical addresses during system integrity checks.

Operation-deterministic write operations for data recovery and integrity checks

Memories using end-to-end data protection using physical location checks are described. In one aspect, a storage device includes non-volatile memory and a controller coupled to the memory. The controller may receive a write instruction including a data word and a logical address, include metadata with the word including error correction data, identify a physical address in a mapping table based on the logical address, generate a tag corresponding to the physical address, and replace the error correction data with the generated tag or a value based thereon before writing the data word to memory. In one embodiment, the controller may generate the tag concurrently with performing a logical error check using the error correction data.

Memories with end-to-end data protection using physical location check

Aspects of a storage device including a memory and a controller are provided which allow for reduction of latency and improve QoS for reads performed in memory locations such as multi-plane dies sharing a bus with the controller. When the controller receives a host read command, the controller sends a read sense command to a memory location to perform a read operation. The controller also sends a status polling command to the memory location to check die status. While the read operation is being performed, and while other read operations are being performed in other memory locations, the controller refrains from polling this memory location and the other memory locations for die status. Rather, the controller continuously toggles a read enable input to the memory location until the read operation is complete and the die status is ready, after which the controller receives data from the memory location.

Read latency reduction through command and polling overhead avoidance

Aspects of a storage device including a controller memory, a die memory, and a plurality of accumulators corresponding to individual DQs are provided for accelerated DQ training and error detection. A controller stores first data in the controller memory, transfers second data to the die memory over an n-bit bus, and receives n bits of the second data from the die memory based on a DQS. The controller then compares n bits of the first data with n bits of the second data to produce n bit results received into respective accumulators, and the controller simultaneously updates different accumulators in response to bit mismatches. During DQ training, if an accumulator value meets a mismatch threshold, the controller modifies a DQS-DQ timing accordingly. During error detection of a read scrambled page, if an accumulator value does not meet an entropy threshold, the controller identifies an error associated with the page.

System for accelerated training of bit output timings

Aspects of a storage device including a memory and a controller are provided which prevent retransmissions of set features commands with identical read voltage threshold offsets for the same die. When the controller receives a first read command for data stored in the memory, the controller identifies a first parameter to modify a first read threshold, and executes a first set features command for modifying the read threshold based on the first parameter. Subsequently, when the controller receives a second read command from the host device for data stored in the memory, the controller identifies a second parameter to modify a second read threshold, and determines whether the first and second parameters are the same. If the parameters are the same, the controller refrains from executing a second set features command for modifying the second read threshold. Thus, the read latency of the storage device may be reduced.

Command optimization through intelligent threshold detection

Read operations are performed in a memory device which efficiently provide baseline read data and recovery read data. In one aspect, on-die circuitry, which is on a die with an array of memory cells, obtains recovery read data before it is requested or needed by an off-die controller. In another aspect, data from multiple reads is obtained and made available in a set of output latches for retrieval by the off-die controller. Read data relative to multiple read thresholds is obtained and transferred from latches associated with the sense circuits to the set of output latches. The read data relative to multiple read thresholds can be stored and held concurrently in the set of output latches for retrieval by the off-die controller.

Multi-level recovery reads for memory

A memory system comprises a plurality of memory dies and a controller (or other control circuit) connected to the memory dies. To reduce the time it takes for the memory system to program data and make that programmed data available for reading by a host (or other entity), as well as persistently store the data in a compact manner that efficiently uses space in the memory system, the data is concurrently programmed as single bit per memory cell (fast programming) and multiple bits per memory cell (compact storage). To accomplish this programming strategy, the controller concurrently transfers data to be programmed to a first memory die and a second memory die. The transferred data is programmed in the first memory die at a single bit per memory cell and in the second memory die at multiple bits per memory cell.

Non-volatile storage system with reduced program transfers

The present disclosure generally relates to data storage devices comprising one or more memory packages. At least one memory package of the storage device comprises a first stack of memory dies coupled together by a first chip select line and a second stack of memory dies coupled together by a second chip select line. Both the first stack and the second stack comprise a plurality of non-volatile memory dies and a dissimilar memory die disposed on top of the plurality of non-volatile memory dies. Within both the first stack and the second stack, the plurality of non-volatile memory dies is a different type of memory than the dissimilar memory die. Additionally, within both the first stack and the second stack, the plurality of non-volatile memory dies is configured to store host data, and the dissimilar memory die is configured to store cached data.

Dual media packaging targeted for SSD usage

The present disclosure discloses a memory device including a controller for bit reordering. The controller receives an input bit sequence including a plurality of bits with a first bit order. The controller identifies a physical location of a non-volatile memory element in the memory device and determines a correspondence between the first bit order and a second bit order based on the physical location. The controller generates an output bit sequence including the plurality of bits with the second bit order based on the correspondence.

Bit reordering for memory devices

Growing community of inventors

Pheonix, AZ, United States of America

Robert W Ellis