Hewlett-Packard Company

Hewlett-Packard Corporation

Robert W Cherry

Mark D Coleman

Byron Alan Alcorn

Brian D Rauchfuss

Erin Antony Handgen

Gary Lewis Taylor

Brad D Reak

A display mode processor which maps pixel inputs into addresses for entries in window-specific color look-up tables in accordance with a predetermined display mode. The display mode processor relieves the central processing unit from video display tasks in a multi-window environment and also supports window-specific attributes such as display mode in addition to window specific color look up tables. This dedicated hardware for video display tasks allows for a more flexible and efficient color display system without sacrificing the overall system performance.

Display mode processor

A circuit for performing window-relative dithering of intensity data comprises a programmable dither cell; circuitry for comparing dither values stored in the dither cell with selected parts of the intensity values and outputting an increment signal in accordance with the results of the comparison; a wrap prevention circuit for preventing the intensity from being incremented if incrementing would cause the intensity to wrap to a low value; and an adder for incrementing the intensity in response to the increment signal, provided it is not inhibited by the wrap prevention circuit. The dither circuit may be advantageously employed in a computer graphics system to dither pixel intensity values.

Window-relative dither circuit

A method of moving blocks of pixel data, including window-identifying data, from a source area to a destination area within a frame buffer in a computer graphics system comprises the steps of: reading a block of pixel data from the source area into a pixel cache memory; combining source tiles with destination tiles in the cache; comparing pixel window identifiers read from the frame buffer with a pixel window identifier previously stored in the memory to determine whether the pixel window identifiers read from the frame buffer match the previously stored pixel window identifier; discarding each pixel whose corresponding window identifier does not match the previously stored window identifier; and updating the frame buffer with the pixel data not discarded.

Method and apparatus for pixel clipping source and destination windows

A three-dimensional pixel cache for use in a computer graphics system comprises source, pattern, and destination tile caches and a barrel shift register, or rotator, that serves as an interface between the tile caches and a frame buffer. The rotator has the capability of performing three types of rotation of data read/written from/to the tile caches horizontal rotation, vertical rotation, and rotation of nibbles within each pixel.

Data rotator for rotating pixel data in three dimensions

Pixel arithmetic and logical units for rendering pixels in graphics systems. Circuits for performing arithmetic operations on raster scan data are provided. The circuits comprise opcode registers for selecting an arithmetic function which transforms pixel value data corresponding to graphics primitives, multiplication circuits interfaced with the opcode registers for multiplying graphics operators with graphics data to obtain transform pixel value data, combining circuits interfaced with the multiplication circuits for adding transform pixel value data to existing pixel value data and processing circuitry interfaced with the combining circuitry for storing overflow data from the combining circuitry when adding transform pixel data overflows the combining circuitry.

Arithmetic and logic processing unit for computer graphics system

A graphics system uses a programmable tile size and shape supported by a frame buffer memory organization wherein (X, Y) pixel map into regularly offset permutations on groups of RAM (Random Access Memory) address and data line assignments. Changing the mapping of (X, Y) pixel addressed to RAM addresses for the groups changes the size and shape of the tiles. A pixel data/partial address multiplexing method based on programmable tile size reduces the number of interconnections between a pixel interpolator and the frame buffer without significantly increasing the number of bus cycles needed to transfer the information. A programmable pipelined shifter allows the dynamic alteration of the mapping between bits of the RGB (red, green, blue) intensity values and the planes of the frame buffer into which those bits are stored, as well as allowing those values to be truncated to specified lengths. Tiles are cached. Tiles for RGB pixel values are cached in an RGB cache, while Z values are cached in a separate cache.

Programmable pipeline for formatting RGB pixel data into fields of

Methods and apparatus for providing pixel brightness correction in monitors. The methods and apparatus disclosed herein provide significant cost reductions in gamma correction circuitry by first degamma correcting pixel value data stored on a frame buffer, and then gamma correcting the degamma corrected pixel value data before the data is stored back on the frame buffer. Circuits for providing pixel brightness correction in a monitor comprise logic circuits for generating upper bits of a data word representing pixel intensity, shifter circuits interfaced with the logic circuits for generating lower bits of the data word representing pixel intensity, and combining circuits interfaced with the logic circuits and the shifter circuits for generating intermediate bits of the data word representing pixel intensity.

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Loveland, CO, United States of America

Robert W Cherry