Chips and Technologies, Llc.

Robert W Catlin

Robert M Pleva

Jefferson Eugene Owen

Rashid N Khan

Frank Spahn

The present invention provides a system whereby the microprocessor and the bus controller in a personal computer can be driven at different frequencies. Furthermore with the present invention the COMMAND DELAY and the WAIT STATE signals on the bus can be adjusted under program control.

Bus controller with different microprocessor and bus clocks and

A support chip includes substantially all the AT core logic, namely most of the X-bus peripherals (except for the keyboard controller), memory controllers, and swapper. The normal AT data paths are altered to reduce the pin count, with a resulting surprising improvement in capability. The chip interfaces to the microprocessor's local address and data buses and provides a 16-bit data bus corresponding to a 16-bit version of the X-bus data portion (XD-bus). External buffers coupled to the XD-bus provide a system data bus (SD-bus) corresponding to the S-bus data portion. The I/O channel is coupled to the SD-bus while system ROM is coupled to the XD-bus. To accommodate the fact that the swapper is internal, the support chip provides independent direction control of the high and low order buffers between the XD-bus and the SD-bus.

Logic support chip for AT-type computer with improved bus architecture

A printed circuit board design capable of accepting both first and second versions of an IC device. First and second IC devices (10, 20) have pins disposed along respective first and second rectangular peripheries (12a-b and 15a-b; 22a-b and 23a-b). Each pin on the first IC device has a functional counterpart pin on the second IC device. The board configuration contains pads in first and second arrays (32a-b and 35a-b; 32a, 32c, 33a-b) that correspond to the pins on the first and second IC devices. At least some of the pads (32b) of the first array do not physically coincide with pads in the second array and are located within the rectangle defined by the second array. Each non-overlapping pad in the first array is connected by a circuit board trace (40) to a respective pad in the second array such that each circuit board trace joins two pads corresponding to counterpart pins.

Printed circuit board design for multiple versions of integrated circuit

In-circuit emulation of a processor that is mounted on a circuit board. The processor (20) is provided with isolation circuitry wherein a particular input signal regime causes all processor outputs to be disabled. The emulator cable (60) terminates in a set of contacts (62a-d, 75) configured to engage the processor pins (12a-d, 25). In the special case of a surface-mount processor, the contacts are mounted to fit over and around the processor and are spring-loaded. Provision is made via at least one of the probe contacts (75) to establish the specific input signal regime at the appropriate processor pin(s) (25) in order to isolate the processor pins from any processor output signals. This prevents any processor output signals from reaching the emulator or the rest of the board logic, thereby allowing the emulator to operate.

In-circuit emulation of a microprocessor mounted on a circuit board

A single semiconductor chip containing both I/O bus controller and DRAM controller functions. A single pin on the chip is used to provide both a zero wait state input to the I/O bus controller and to provide a local bus access (LBA) signal for inhibiting both the I/O bus controller and the DRAM controller when an external device is doing an I/O or memory operation on the local bus. Logic isprovided to produce an inhibit signal to the I/O bus controller in response to the LBA signal. Another logic circuit is provided to inhibit the DRAM controller in response to the LBA signal only when there is a memory cycle signal from the microprocessor. The use of the single pin is possible since the zero wait state isgnal will only appear during the latter part of an I/O or memory cycle, which is mutually exclusive with the start of an I/O or memory cycle, which is the only time the LBA signal will appear.

Apparatus for allowing external control of local bus read using zero

A memory controller which can map EMS addresses into the DRAM behind video RAM addresses or other reserved areas of memory. A single chip has both a DRAM decoder and an EMS decoder operating in parallel. A DRAM decoder examines received addresses and provides an enable signal to a DRAM timing circuit if the address is within the DRAM range and not for a reserved group of addresses. A separate EMS decoder provides a translated address when a received address is within an EMS window. The EMS decoder also provides an EMS timing signal to the DRAM timing circuit.

Memory controller for using reserved DRAM addresses for EMS

A printed cirucit board design capable of accepting both first and second versions of an IC device. First and second IC devices (10, 20) have pins disposed along respective first and second rectangular peripheries (12a-b and 15a-b; 22a-b and 23a-b). Each pin on the first IC devices has a functional counterpart pin on the second IC device. The board configuration contains pads in first and second arrays (32a-b and 35a-b; 32a, 32c, 33a-b) that correspond to the pins on the first and second IC devices. At least some of the pads (32b) of the first array do not physically conicide with pads in the second array and are located within the rectangle defined by the second array. Each non-overlapping pad in the first array is connected by a circuit board trace (40) to a respective pad in the second array such that each circuit board trace joins two pads corresponding to counterpart pins.

An improved memory controller which can support varying numbers of banks of memory without requiring any more RAS output pins than are necessary for a minimum number of banks of memory. The memory controller chip has N RAS output pins. An internal decoder selects one of N decode outputs after decoding internally provided coded RAS addresses. A timing signal is generated to control the duration of the selected decoder output to provide the proper pulse length for the RAS signal. An internal multiplexer, with its outputs coupled to the RAS output pins, selects either the N decode outputs from the decoder or the timing signal and the internally provided addresses directly.

Apparatus for selectively providing RAS signals or RAS timing and coded

An integrated circuit chip that facilitates connecting peripheral devices to an MCA Micro Channel Architecture bus system. With the present invention manufacturers of adapter boards and cards can easily interface peripheral devices to an MCA bus. With the present invention the MCA interface is segmented in a different manner than it is segmented in prior art adapters. In the approach utilized with the present invention the interface has been partitioned so that the microchannel signals and the protocol signals common to all functions are contained on an interface chip. The present interface integrated chip combines (a) command decode circuitry for receiving coded signals from the MCA bus and for generating decoded command signals for peripheral devices, (b) pin control circuitry which controls multi-function pins, (c) bus arbitration control circuitry, (d) POS Programmable Option Select register control circuitry to facilitate adapter identification support, (e) ready logic circuitry to facilitate synchronous ready signal generation, (f) circuitry to facilitate device error reporting, (g) external data buffer control, (h) bus response signal generation circuitry, and (j) circuitry to support memory and I-O relocation. The above combination of functions is provided on a single integrated circuit thereby efficiently utilizing the limited number of I-O pins available on the integrated circuit.

Personal computer bus interface chip with multi-function address

A memory controller which can map expanded memory space (EMS) addresses into the dynamic random access memory (DRAM) behind video random access memory (RAM) addresses or other reserved areas of memory. A single chip has both a DRAM decoder and an EMS decoder operating in parallel. A DRAM decoder examines received addresses and provides an enable signal to a DRAM timing circuit if the address is within the DRAM range and not for a reserved group of addresses. A separate EMS decoder provides a translated address when a received address is within an EMS window. The EMS decoder also provides an EMS timing signal to the DRAM timing circuit.

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Santa Clara, CA, United States of America

Robert W Catlin