Freescale Semiconductor,inc.

Everspin Technologies, Inc.

Motorola Corporation

Other

Robert W Baird

Young Sir Chung

Mark A Durlam

Edouard De Frésart

Jiang-kai Zuo

Gregory W Grynkewich

Bradley Neal Engel

Won Gi Min

Eric John Salter

Gordon P Lee

Steven L Merchant

Phillipe Dupuy

Ganming Qin

William J Dauksher

David P Mancini

Edouard D deFresart

Steven R Young

Donald F Weston

Charles J Baird

Theodore J Beatty

Patricia Hopper

Electronic elements with very low resistance back-side coupling are provided by forming one or more narrow trenches or pipes, preferably dielectric lined, in front sides of substrates, filling the trenches or pipes with a conductor having a coefficient of expansion not too different from that of the substrate but of higher conductivity, forming an epitaxial SC layer over the front side of the substrate in Ohmic contact with the conductor the trenches or pipes, forming various semiconductor (SC) devices in the epi-layer, back grinding the substrate to expose bottoms of the conductor filled trenches or pipes, and providing a back-side conductor contacting the conductor in the trenches or pipes. For silicon SCs, tungsten is a suitable conductor for filling the trenches or pipes to minimize substrate stress. Series ON-resistance of the elements due to the substrate resistance is substantially reduced.

Semiconductor devices with low resistance back-side coupling

In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.

Ultra-thin die and method of fabricating same

Electronic elements () with very low resistance back-side coupling are provided by forming one or more narrow trenches or pipes (), preferably dielectric lined, in front sides () of substrates ('), filling the trenches or pipes with a conductor () having a coefficient of expansion not too different from that of the substrate (&#x2032;) but of higher conductivity, forming an epitaxial SC layer () over the front side () of the substrate (&#x2032;) in Ohmic contact with the conductor () in the trenches or pipes (), forming various semiconductor (SC) devices () in the epi-layer (), back grinding the substrate (&#x2032;) to expose bottoms () of the conductor filled trenches or pipes (), and providing a back-side conductor () contacting the conductor () in the trenches or pipes (). For silicon SCs, tungsten is a suitable conductor () for filling the trenches or pipes () to minimize substrate stress. Series ON-resistance of the elements () due to the substrate resistance is substantially reduced.

Methods for forming semiconductor devices with low resistance back-side coupling

An antifuse element () includes a substrate material () having an active area () formed in an upper surface, a gate electrode () having at least a portion positioned above the active area (), and a gate oxide layer () disposed between the gate electrode () and the active area (). The gate oxide layer () includes one of a gate oxide dip () or a gate oxide undercut (). During operation a voltage applied between the gate electrode () and the active area () creates a current path through the gate oxide layer () and a rupture of the gate oxide layer () in a rupture region (). The rupture region () is defined by the oxide structure and the gate oxide dip () or the gate oxide undercut ().

Antifuse elements

Methods for forming semiconductor structures are provided for a semiconductor device employing a superjunction structure and overlying trench with embedded control gate. An embodiment comprises forming interleaved first and second spaced-apart regions of first and second semiconductor materials of different conductivity type and different mobilities so that the second semiconductor material has a higher mobility for the same carrier type than the first semiconductor material, and providing an overlying third semiconductor material in which a trench is formed with sidewalls having thereon a fourth semiconductor material that has a higher mobility than the third material, adapted to carry current between source regions, through the fourth semiconductor material in the trench and the second semiconductor material in the device drift space to the drain. In a further embodiment, the first and third semiconductor materials are relaxed materials and the second and fourth semiconductor materials are strained semiconductor materials.

Superjunction trench device formation methods

Semiconductor structures (---) and methods (-) are provided for a semiconductor devices employing strained () and relaxed () semiconductors, The method comprises, forming () on a substrate () first (-) and second (-) regions of a first semiconductor material () of a first conductivity type and a first lattice constant spaced apart by a gap or trench (), filling () the trench or gap () with a second semiconductor material () of a second, conductivity type and a second different lattice constant so that the second semiconductor material () is strained with respect to the first semiconductor material () and forming () device regions (, S, G, D) communicating with the first () and second () semiconductor materials and adapted to provide device current () through at least part of the strained second semiconductor material () in the trench (). In a preferred embodiment, the relaxed semiconductor material isSi:Ge and the strained semiconductor material is substantially Si.

Strained semiconductor power device and method

An embodiment of an MOS device includes a semiconductor substrate of a first conductivity type, a first region of the first conductivity type having a length Land a net active dopant concentration of about N, a pair of spaced-apart body regions of a second opposite conductivity type and each having a length Land a net active dopant concentration of about N, channel regions located in the spaced-apart body regions, source regions of the first conductivity type located in the spaced-apart body regions and separated from the first region by the channel regions, an insulated gate overlying the channel regions and the first region, and a drain region of the first conductivity type located beneath the first region. In an embodiment, (L*N)=k*(L*N), where khas a value in the range of about 0.6&#x2266;k&#x2266;1.4.

Superjunction power MOSFET

Semiconductor structures and methods are provided for a semiconductor device () employing a superjunction structure () and overlying trench () with embedded control gate (). The method comprises, forming (--) interleaved first (----, etc.) and second (---, etc.) spaced-apart regions of first () and second () semiconductor materials of different conductivity type and different mobilities so that, in a first embodiment, the second semiconductor material () has a higher mobility for the same carrier type than the first semiconductor material (), and providing (-) an overlying third semiconductor material () in which a trench () is formed with sidewalls () having thereon a fourth semiconductor material () that has a higher mobility than the third material (), adapted to carry current () between source regions (), through the fourth () semiconductor material in the trench () and the second semiconductor material () in the device drift space () to the drain (). In a further embodiment, the first () and third () semiconductor materials are relaxed materials and the second () and fourth () semiconductor materials are strained semiconductor materials.

Superjunction trench device and method

Means and methods are provided for trench TMOS devices (-), comprising, providing a first semiconductor () of a first composition having an upper surface (), with a body portion () proximate the upper surface (), a drift portion () spaced apart from the upper surface () and a trench () having sidewalls () extending from the upper surface () into the drift portion (). A second semiconductor () adapted to provide a higher mobility layer is applied on the trench sidewalls () where parts () of the body portion () are exposed. A dielectric () covers the higher mobility layer () and separates it from a control gate () in the trench (). Source regions () formed in the body portion () proximate the upper surface () communicate with the higher mobility layer (). When biased, source-drain current () flows from the source regions () through gate induced channels () in the higher mobility layer () and into the drift portion () where it is extracted by a drain () or other connection coupled to the drift portion ().

Trench power device and method

An antifuse element () and method of fabricating the antifuse element, including a substrate material () having an active area () formed in an upper surface, a gate electrode () having at least a portion positioned above the active area (), and a gate oxide layer () disposed between the gate electrode () and the active area (). The gate oxide layer () including the fabrication of one of a gate oxide dip () or a gate oxide undercut (). During operation a voltage applied between the gate electrode () and the active area () creates a current path through the gate oxide layer () and a rupture of the gate oxide layer () in a rupture region (). The rupture region () defined by the oxide structure and the gate oxide dip () or the gate oxide undercut ().

Antifuse element and method of manufacture

An integrated circuit device is provided which comprises a substrate, a conductive line configured to experience a pressure, and a magnetic tunnel junction ('MTJ') core formed between the substrate and the current line. The conductive line is configured to move in response to the pressure, and carries a current which generates a magnetic field. The MTJ core has a resistance value which varies based on the magnetic field. The resistance of the MTJ core therefore varies with respect to changes in the pressure. The MTJ core is configured to produce an electrical output signal which varies as a function of the pressure.

Magnetic tunnel junction pressure sensors and methods

Methods and apparatus are provided for sensing physical parameters. The apparatus comprises a magnetic tunnel junction (MTJ) and a magnetic field source whose magnetic field overlaps the MTJ and whose proximity to the MTJ varies in response to an input to the sensor. The MTJ comprises first and second magnetic electrodes separated by a dielectric configured to permit significant tunneling conduction therebetween. The first magnetic electrode has its spin axis pinned and the second magnetic electrode has its spin axis free. The magnetic field source is oriented closer to the second magnetic electrode than the first magnetic electrode. The overall sensor dynamic range is extended by providing multiple electrically coupled sensors receiving the same input but with different individual response curves and desirably but not essentially formed on the same substrate.

Magnetic tunnel junction sensor

An integrated circuit device is provided which includes a heat source disposed in a substrate, and a Magnetic Tunnel Junction ('MTJ') temperature sensor disposed over the heat source.

Magnetic tunnel junction temperature sensors

Techniques of sensing a temperature of a heat source disposed in a substrate of an integrated circuit are provided. According to one exemplary method, a Magnetic Tunnel Junction ('MTJ') temperature sensor is provided over the heat source. The MTJ temperature sensor comprises an MTJ core configured to output a current during operation thereof. The value of the current varies based on a resistance value of the particular MTJ core. The resistance value of the MTJ core varies as a function of the temperature of the heat source. A value of the current of the MTJ core can then be associated with a corresponding temperature of the heat source.

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Gilbert, AZ, United States of America

Robert W Baird