Nxp B.v.

Robert Van Veldhoven

John M Pigott

Klaus Reimann

Anco Heringa

Olaf Wunnicke

Edwin Jan Schapendonk

Jan Willem Slotboom

Maarten Jelmar Molendijk

Selcuk Ersoy

Jaap Ruigrok

Harry Neuteboom

Victor Zieren

Fabio Sebastiano

Erik Olieman

Alphons Litjes

Jörg Kock

Jan Claes

Ralf Van Otten

Leon Van Der Dussen

Dobson Paul Parlindungan Simanjuntak

Rui Quan

Pieter Van Der Zee

Carel Dijkmans

Ben Kup

Dmitrij Andreevits Sjwed

Khalid Mabtoul

Victor Pecanins Martinez

A device may include an input terminal configured to receive an analog input signal. A device may include an output terminal configured to output a digital signal x, wherein the digital signal x includes a digital approximation of the analog input signal. A device may include an error correction system connected to the ADC, the error correction system including a first input terminal configured to receive an Nth powered version of the digital signal x, wherein N is a whole number equal to or greater than two, wherein the error correction system is configured to: use the Nth powered version of the digital signal x to determine a correction value; and modify the digital signal x to generate a corrected digital signal by applying the correction value to compensate for analog-to-digital conversion errors occurring within the ADC.

ADC error compensation using powers of ADC output

A device may include a sigma-delta analog-to-digital converter (ADC) configured to convert an analog input signal to a digital signal that is a digital approximation of the analog input signal. A bitstream modifier is configured to receive the digital signal, output a first signal that is based on the digital signal at a first output terminal and output a first difference signal at a second output terminal that includes a first difference value between a first value of the digital signal and a second value of the digital signal. The second value is immediately prior to the first value in the digital signal. An error correction system is configured to receive the first signal, receive the first difference signal, use the first signal and the first difference signal to determine a correction value, and modify the digital signal to generate a corrected digital signal by applying the correction value.

Inter-symbol interference compensation for analog-to-digital converter

An analog to digital circuit that includes a feedback circuit with a return to open (RTO), digital to analog converter (DAC) that provides an analog signal that is indicative of an output of an ADC component of the ADC. During a data phase, the output of the DAC is provided to a combiner input through a resistive circuit. The combiner also receives an analog input signal at another input and provides a combined output signal to the ADC component. During a reset phase, the output of the DAC is provided to the combiner through a lower resistance bypass circuit to bypass the resistive circuit.

Return to open DAC with resistor bypass on reset

A system includes a time-interleaved analog-to-digital converter (TI ADC). The TI ADC includes a plurality of ADC units connected in parallel between an input terminal and an output terminal of the time-interleaved ADC. An ADC tag generator is configured to output a first identifier of a first ADC unit of the plurality of ADC when the first ADC unit is enabled. An error correction system is configured to receive a first digital signal from the output terminal of the time-interleaved ADC, receive the first identifier of the first ADC unit from the ADC tag generator, modify the first digital signal to generate a first corrected digital signal by compensating for first analog-to-digital conversion errors occurring within the first ADC unit by applying a first error correction scheme that is associated with the first ADC unit, and output the first corrected digital signal.

Time interleaved analog-to-digital converter with ADC unit correction

An interface circuit includes an analogue to digital converter having an input configured to receive an input signal having an unknown DC bias voltage via an input resistance and provide an output signal to an ADC feedback loop. The ADC feedback loop includes a digital filter arranged to digitally filter the fedback output signal. A digital to analogue converter (DAC) forming a DC feedback loop with the ADC and arranged to convert the digitally filtered fedback output signal to an analogue signal that is provided to the input of the ADC, wherein the analogue signal that is provided to the input of the ADC is arranged to include a DC bias component that is comparable to a DC bias component of a current of the input signal passing through the input resistor.

Interface circuit and method for providing DC bias voltage correction

A continuous-time delta-sigma modulator, CTDSM () is described that comprises: an operational transconductance amplifier, OTA, () having an input port () configured to receive an analog input signal and an output port (); an input low pass filter network comprising at least one input resistor, R1, () at least one first shunt capacitor, C1, () and at least one feedback resistor, Rdac () connected to the input port of the OTA; an output filter network comprising a shunt second resistor, R2, () in parallel to a second shunt capacitor, C2, (), and coupled to the output port () of the OTA; a quantizer () connected to the output filter network and having at least one output connected to the input port of the OTA via the at least one feedback resistor, Rdac; and wherein the input and output port of the OTA connected by a third feedforward-feedback capacitor, C3, () arranged to provide a positive feedback around the OTA.

Continuous-time delta-sigma modulator, integrated circuit and method therefor

A sigma-delta ADC is described including a passive filter with an input coupled to the ADC input and a filter output. A gain stage has an input connected to the filter output. A quantiser has an input connected to the gain stage output and a quantiser output. The passive filter includes a first filter resistor between the filter input and the filter output and a filter capacitor having first terminal coupled to the filter output. A feedback resistor is coupled between the quantiser output and the filter output and receives a negative of the value of the output to provide negative feedback to the filter output. The gain stage has a capacitor and resistor in series, and a gain element connected to the gain stage input and an output connected to the gain stage output. One terminal of the gain stage capacitor is connected to the gain element output.

Sigma-delta analog-to-digital converter

An amplifier including a P-channel transistor having current terminals coupled between a first node and a second node and having a control terminal coupled to a third node receiving an input voltage, an N-channel transistor having current terminals coupled between a fourth node developing an output voltage and a supply voltage reference and having a control terminal coupled to the second node, a first resistor coupled between the first node and a supply voltage, a second resistor coupled between the first and fourth nodes, and a current sink sinking current from the second node to the supply reference node. The amplifier may be converted to differential form for amplifying a differential input voltage. Current devices may be adjusted for common mode, and may be moved or added to improve headroom or to improve power supply rejection. Chopper circuits may be added to reduce 1/f noise.

Amplifier with low component count and accurate gain

A digital signal generator apparatus and method is described. The digital signal generator includes a counter, an integrator and a comparator. The counter counts up or down from an initial counter value dependent on a counter control input. The comparator has a first input coupled to the counter output, a threshold input and a comparator output coupled to the counter control input. The integrator has an input coupled to the counter output and an output coupled to the digital signal generator output. The digital signal generator determines the count direction after the initial direction dependent on the comparison between a threshold value applied to the threshold input and the counter output value. The digital signal generator may implement the generation of a waveform having an approximation to a raised cosine function. The generated waveform may be used for audio artefact reduction in an audio amplifier during mute or unmute operations or during power up power down operations.

Digital signal generator for audio artefact reduction

A passive sigma-delta modulator including first modulator loop, a second modulator loop, and a digital combiner providing an output signal. The first modulator loop includes a first quantizer, a first passive summing junction, a first continuous-time passive analog loop filter, and a first feedback path. The second modulator loop includes a second quantizer, analog transfer circuitry, a second continuous-time passive summing junction, a second passive analog loop filter, a second feedback path, and digital transfer circuitry having a gain that is substantially a reciprocal of the analog transfer circuitry. A digital noise cancelation filter may be located between the first quantizer and the digital combiner, or an analog noise cancelation filter may be provided within the second modulator loop. Single-ended or differential configurations are contemplated.

Dual loop passive sigma-delta modulator

Analog to digital conversion errors caused by non-linearities or other sources of distortion in an analog-to-digital converter are compensated for by use of a machine learning system, such as a neural network. The machine learning system is trained based on simulation or measurement data, which utilizes a filtered output of the analog-to-digital converter that has less distortion errors than the unfiltered output of the analog-to-digital converter. The effect on the analog to digital conversion errors by Process-Voltage-Temperature parameters may be incorporated into the training of the machine learning system.

Training a machine learning system for ADC compensation

The present application relates to an EQ circuit, a method of operating it and a system comprising the EQ circuit and an ADC. The EQ circuit has a configurable load section, which is provided for selectively exposing one of a plurality of distinct loads to a reference source connected to a reference voltage signal input of the equalization circuit, and a logic section, which is arranged to accept a state signal from the ADC and to selectively connect one distinct load out of the plurality of distinct loads in response to the state signal. The state signal is indicative of an actual operation state of the ADC.

Equalization circuit, a method of operating an equalization circuit and a system comprising an equalization circuit and an ADC

A digital-to-analog converter (DAC) includes a plurality of resistive elements connected together in series to form a ring of resistive elements. A node is formed by each of the connections of adjacent resistive elements of the ring. Groups of parallel-connected switches are coupled to each node. A first switch of the group of switches is for selectively coupling a first power supply voltage terminal to the node. A second switch of the group of switches is for selectively coupling a second power supply voltage to the node. A third switch of the group of switches is for selectively coupling an output terminal to the node. A differential or single-ended analog output may be provided. Mismatch induced error is removed using a mismatch error shaping technique that shapes the errors outside a pass-band.

Resistor ladder digital-to-analog converter with mismatch correction and method therefor

A magnetic field sensor is disclosed for providing an output signal in response to an external magnetic field. The sensor comprises a primary magnetic field transducer for producing a primary signal in response to the external magnetic field and having a first magnetic field saturation characteristic; a secondary magnetic field transducer for producing a secondary signal in response to the external magnetic field and having a second magnetic field saturation characteristic. The first magnetic field saturation characteristic is different from the second magnetic field saturation characteristic. The sensor is configured to use the secondary signal to correct for errors in the output signal arising from saturation of the primary transducer.

Magnetic field sensor having primary and secondary magnetic field transducers with different magnetic field saturation characteristics

A sensor system is disclosed. The sensor system includes a first sensor path comprising a first sensing element and a second sensing element being connected in series between a first supply terminal and a second supply terminal and an intermediate node connected in between the first supply terminal and the second supply terminal, a second sensor path comprising a third sensing element and a fourth sensing element connected in series between the first supply terminal and the second supply terminal, a first reference node connected in between the first supply terminal and the second supply terminal, and a second reference node connected in between the first supply terminal and the second supply terminal, and a processing unit to receive an input signal from the intermediate node, a first reference signal from the first reference node, and a second reference signal from the second reference node.

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Valkenswaard, Netherlands

Robert Van Veldhoven