Zarlink Semiconductor Limited

Robert Van Der Valk

Simon John Skierszkan

A timing circuit for generating clock signals, includes an acquisition digital phase locked loop with a wide capture range for closely following an input signal with its associated disturbances. An output digital phase locked loop having a slow response relative to the acquisition phase locked loop tracks an output of the acquisition phase locked loop to generate an output signal for the timing circuit.

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Rotterdam, Netherlands

Robert Van Der Valk