Bull Hn Information Systems, Inc.

Honeywell Information Systems Inc.

Robert V Ledoux

Richard P Kelly

James W Keeley

Jian-Kuo Shen

Virendra S Negi

David E Cushing

Chester M Nibby, Jr

Forrest M Phillips

Deborah K Staplin

The decoding of certain instructions cause an instruction unit of a production line data processing system to stall. Instructions still in the production line are executed, but no new instructions are sent into the production line until the instruction that caused the stall condition is executed. The execution of the instruction that caused the stall is completed by an execution unit taking over control of an address unit.

Control store addressing from multiple sources

A data processing system includes cache memories for storing instructions and operands. An execution unit stores instructions in an instruction FIFO, operands in a data FIFO and offsets in an offset FIFO. Offsets indicate the location of operands relative to a memory word boundary. Instructions read from the instruction FIFO are applied to a control store subsystem which reads out a firmware word. Specified firmware bits condition multiplexers in the data path to align the operands on the fly during the execution of the instruction.

Apparatus for generating first and second selection signals for aligning

During the execution of an instruction by an execution unit, the instruction is stored in an instruction register, the operand including its ring number is stored in a data register and the ring number developed by the Virtual Memory Management Unit is stored in a ring effective register. The instruction addresses a control store which stores a firmware word in a control store register. A firmware field is decoded to generate a plurality of ring control signals. The ring numbers from the data and ring effective registers are compared and an effective ring number is generated. Depending on the states of the secure process signal, the ring control signals and the relative value of the ring numbers, the effective ring number is binary 00 or the larger ring number.

Ring reduction logic using parallel determination of ring numbers in a

A separate register file memory is included in at least two units of a pipelined processor which are located on separate integrated circuit chips. The register file memories of the units are interconnected so as to share certain input data register stages to enable updating to take place within a minimum of time. Each unit has a microprogrammed control unit which automatically provides update commands during the unit's cycles of operation. The signals from each microprogrammed control unit are applied to both register file memories enabling both memories to be updated during successive cycles of operation and thereby function collectively as one unit. This ensures that both units have access to the same most recently updated user visible information enabling both units to complete the execution of different instructions entering pipeline.

Mechanism for automatically updating multiple unit register file

A firmware controlled microprocessor plugged into a printed circuit board received firmware signals from a control store mounted on the printed circuit board. The number of pins required for transferring firmware signals is reduced by time sharing pins with firmware signal required for the full cycle of operation and firmware signal required only during the second half of the cycle of operation.

Means for transferring firmware signals between a control store and a

A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test apparatus coupled to the control apparatus and operates to selectively alter the operational states of the cache levels in response to commands received from a central processing unit for enabling testing of such control apparatus in addition to the other cache control areas.

Test apparatus for testing a multilevel cache system with graceful

A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test control apparatus which couples to the directory error checking apparatus operates to selectively enable and disable the directory error checking circuits in response to commands received from a central processing unit so as to enable the testing of the cache directory and other portions of the cache system using common test routines.

Enable/disable control checking apparatus

A multilevel set associative cache system whose directory and cache store organized into levels of memory locations. Round robin replacement apparatus is used to identify in which level information is to be replaced. The directory includes error checking apparatus for generating address check bits which are written into directory locations together with addresses. Control apparatus in response to error signals from the error checking apparatus degrades cache operation to those levels detected to be free from errors. Test error mode control apparatus which couples to the replacement and check bit apparatuses causes the address check bits to be selectively forced to incorrect values in response to commands received from a central processing unit enabling the verification of both the checking and control apparatus without interference from other operations initiated by the central processing unit.

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Litchfield, NH, United States of America

Robert V Ledoux