Infineon Technologies Richmond, LP

Robert Trahan

Ulrich Zimmerman

Allen Chu

A fuse configuration for a semiconductor storage device is provided. The fuse configuration includes a first electrode formed in a dielectric layer, the first electrode having a first cross-sectional area defined by a first perimeter; a fuse element, or isolating layer, for coupling the first electrode to a second electrode; and the second electrode having a second cross-sectional area defined by a second perimeter, the first perimeter of the first electrode being larger than the second perimeter. By employing this modified capacitor layout, the fuse element, or isolating layer, will never come into contact with an edge of the first electrode, and thus eliminate a high electric field region from the fuse layout and reliability issues of the prior art fuse configurations. A method for forming the fuse configuration is also provided.

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Glen Allen, VA, United States of America

Robert Trahan