Emc Corporation

Smart Modular Technologies, Inc.

Robert Tower Frey

Chao Zhang

Kelvin Alberto Marino

Santosh C Lolayekar

Yu-Ping Cheng

Renato E Maranon

Jinying Shen

Wan-Hui Lee

Joshua Harris Brooks

Poulo Kuriakose

Rajesh Ananthanarayanan

Hawkins Yao

Anoop R Hegde

Enyew Tan

Sunil K Asthana

Systems and methods for enabling serial attached Non-Volatile (NV) memory are provided. In some embodiments, a method of operation of a computing system including: in an NV Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a NV Controller unit (NVC), and a serial host interface, the method includes: receiving a request for data on the serial host interface and providing the requested data, from the volatile memory device with data, on the serial host interface. The method also includes: detecting a disruptive volatile memory event; copying the data of the volatile memory device to the NV device based on the disruptive volatile memory event; and restoring the data of the volatile memory device from the NV device. In this way, Dynamic Random-Access Memory (DRAM) level endurance and speed/latency can be provided while making it NV.

Serial attached non-volatile memory

A deaggregated computing system having a memory centric computing storage controller can transfer data from a source to a destination node while dynamically updating a transfer route between them. The transfer route can be recalculated based on the current conditions of the routing nodes between the source and destination. Recalculating the transfer route can be based on power status, bandwidth, in-use status, current capacity, or failure conditions. The deaggregated computing system can include one or more processor units coupled to one or more storage and memory units all connected by the memory centric computing storage controller that can route control and data packets between the processor units and the storage and memory units. The processor units and the storage units can be connected by a combination of serial data communication links and a data storage fabric network.

Memory centric computing storage controller system

A memory management system, and method of operation thereof, includes: a primary device of a resilient storage module configured as a boot device for booting a computer system; an operational status received from the computer system; a secondary device of the resilient storage module configured as the boot device based on the operational status indicating a non-operational state; and a memory module controller of the resilient storage module for initiating a reboot operation using the secondary device as the boot device.

Memory management system with multiple boot devices and method of operation thereof

An integrated circuit system, and a method of operation thereof, including: a memory unit having a volatile memory device with data and a non-volatile controller unit; a memory unit controller of the non-volatile controller unit for receiving a snoop signal for indicating an error; a non-volatile device of the memory unit for synchronously receiving data of the volatile memory device based on the snoop signal, the data autonomously copied without any intervention from outside the memory unit to prevent loss of the data; and an in-band command received by the memory unit, for autonomously restoring the data to the volatile memory device from the non-volatile device without any intervention from outside the memory unit.

Computing system with backup and recovery mechanism and method of operation thereof

A method of manufacture of the memory management system includes: fabricating a dual in-line memory module carrier; mounting a volatile memory device on the dual in-line memory module carrier; mounting a non-volatile memory on the dual in-line memory module carrier on a side opposite the volatile memory device; mounting an uninterruptible power supply on the dual in-line memory module carrier for maintaining a memory module power when a system power input decays; and mounting a controller logic integrated circuit on the dual in-line memory module carrier coupled to the volatile memory device, the non-volatile memory, and the uninterruptible power supply for copying data content of the volatile memory device to the non-volatile memory when the uninterruptible power supply detects the decay of the system power input to a first cross-over level.

Memory management system with power source and method of manufacture thereof

A method for operating a computing system includes: monitoring a central interface for a power event; accessing a high-speed memory for pre-shutdown data; accessing a non-volatile memory during the power event for the pre-shutdown data previously stored on the high-speed memory; selecting a multiplexer for allowing external access to the high-speed memory; and formatting the pre-shutdown data in the non-volatile memory for access through a non-disruptive interface.

Computing system with non-disruptive fast memory restore mechanism and method of operation thereof

Systems and methods in accordance with various embodiments relate to a storage switch including task processing synchronization. In embodiments of the present invention, the packet processing units may generate and store Task Index and Generation Count information that prevents the processing of expired commands or responses. Additionally or alternatively, embodiments of the present invention may further employ timeout sequences to prevent previous instances of a stale task resource from disrupting the current use of the task resource.

Storage switch task processing synchronization

A storage switch in accordance with an embodiment of the invention is a highly scalable switch that allows the creation of a SAN that is easy to deploy and that can be centrally managed. Moreover, such a storage switch also allows the deployment of a global infrastructure, allowing the resources of the SAN, such as storage devices, to essentially be positioned anywhere on the globe. Further, such a storage switch allows a multi-protocol SAN, e.g., one that includes both iSCSI or Fibre Channel, and processes data packets at 'wire speed.' To further enable wire-speed processing, a switch in accordance with the invention has 'intelligence' distributed to each of its linecards, through which it classifies packets into data and control packets, it performs virtualization functions, and it performs protocol translation functions. A switch in accordance with the invention further performs serverless storage services such as mirroring, snapshot, and replication.

Virtualization in a storage system

A storage switch is disclosed that facilitates mirroring of data. For example, a target is mirrored when an identical (or almost identical) copy of the data is stored in two or more separate physical data stores. Because the various data stores may not be homogenous, they may provide for different burst sizes. To accommodate the different burst sizes, the switch provides different sequence counts for data packets sent to the different data stores that store the mirrored data.

Storage switch mirrored write sequence count management

A switch including a processor and method for monitoring bandwidth in the storage switch. The switch includes at least one physical port coupling at least one target and at least one initiator via the physical port. The monitoring method may include the steps of determining whether congestion occurs on the physical port and assigning a weight to bandwidth usage between the initiator and the target based on a minimum and maximum bandwidth settings for each target. The switch may further include a step of controlling bandwidth usage by each of said at least two targets based on minimum and maximum bandwidth settings for each of the targets.

Storage switch traffic bandwidth control

Storage switch for storage area network

Systems and methods can provide mirrored virtual targets and online synchronization and verification of the targets while avoiding deadlock, inconsistencies between members of the target, and false verification failures. A lock within the storage switch can limit the number of outstanding commands for a physical target to one during synchronization and verification operations. In one embodiment, a lock can be implemented as one or more resource tables maintaining an indication of the number of transfer ready signals available from physical targets. During typical write operations, deadlock can be avoided by determining whether each physical target for the mirrored operation can issue a transfer ready signal prior to issuing a command to the physical target. When a synchronization or verification operation begins, the maximum available number of transfer ready signals for each target can be decremented to one in order to limit the total number of outstanding commands for each target to one.

Systems and methods to avoid deadlock and guarantee mirror consistency during online mirror synchronization and verification

Systems and methods in accordance with various disclosed embodiments can manage a mirrored virtual target to synchronize the members of the virtual target and/or to verify that the members of the virtual target are synchronized. In one embodiment, a mirrored virtual target is synchronized by first provisioning at least one first internal virtual logical unit (IVLU) corresponding to at least one destination target of the mirrored target and a second IVLU corresponding to a source target of the mirrored target. A write command is first issued, via one or more internal virtual logical units, to each of the destination target members of the mirrored target. When each destination target is available to receive data, as evidenced by a returned transfer ready signal, a read command is provided to the source target via the second internal virtual logical unit. In this manner, a data path between the source and destination targets is established prior to reading data from the source target. Accordingly, the data can be read from the source target, converted to write data, and routed to the destination targets at line speed without buffering of the data. A similar process is provided to verify that the members of a mirrored target are synchronized. In one embodiment, a system and method is provided to manage incoming commands for the mirrored target while synchronizing or verifying synchronization of the mirrored target. Incoming commands can be queued as they are received and provided to the mirrored target when pending synchronization or verification commands are completed.

Online initial mirror synchronization and mirror synchronization verification in storage area networks

Systems and methods in accordance with various embodiments can detect and alleviate potential or actual deadlock of a storage switch or storage area network when attempting to write data to a mirrored virtual target. In accordance with one embodiment, a timer is started when a storage switch routes a write command to the physical targets corresponding to a virtual target of the write command. If each physical target does not return a transfer ready resource within a predetermined timeout period, the switch determines that a potential or actual deadlock has occurred. An abort command is sent to each of the physical devices. The abort command can clear the command from the targets and also free any allocated transfer ready resources. After receiving an acceptance response from each physical target, the state of the write command at the switch can be cleared. The write command can then be re-issued to the physical devices. In one embodiment, a queue depth for the virtual target can be lowered after failing to receive transfer ready resources from each target. By decreasing the queue depth, the maximum number of commands the switch will process for a virtual target is decreased to decrease the probability of future deadlock. In one embodiment, the queue depth is increased after no deadlock is detected for a period of time.

Growing community of inventors

Milpitas, CA, United States of America

Robert Tower Frey