International Business Machines Corporation

North Carolina State University

Robert Thomas Bailis

Charles Steven Lingafelt

Charles Edward Kuhlmann

Ann Marie Rincon

David John Jensen

Thomas L Bonds, Jr

Brian Scott Oakley

Michael James Ward

Roy Lee Draughn

Alvin Dean Genzlinger

Brian Flynn

Alan Kinlaw

Ian Jester

Tom Butler

Carl Taylor

A telescoping box includes a lid. The upper section of the box includes lids which are frictionally engagable therewith. The lids include speaker assemblies as part of each lid. The lids are removable and include connection points for audio signal sources such as MP3 players.

Portable box for carrying items

An application specific integrated circuit (ASIC) is disclosed. The ASIC includes a standard cell. The standard cell includes a plurality of logic functions. The ASIC also includes at least one bus coupled to at least a portion of the logic functions and a plurality of internal signals from the plurality of logic functions. Finally, the ASIC includes a field programmable (FP) function coupled to the at least one bus and at least a portion of the plurality of internal signals. The FP function provides access to internal signals for observation and control. An ASIC using a field programmable gate array (FPGA) function within a standard cell design is utilized to create an internal-to-the-ASIC bridging of internal signals to observe and control of the internal signals of the ASIC. By the placement of logic, which expresses a test program, into the FPGA function that manipulates the I/O pins and/or other functional entities of interest, the ASIC function and/or surrounding logic can be easily verified. In addition, through this system, internal and/or system (external-to-the-ASIC) conditions can be observed. Furthermore, a sequence of resets to different functional blocks can be executed utilizing a system and method in accordance with the present invention. Finally, through this system the end user of the ASIC could write their own error condition correction FPGA code which would communicate using protocols of the existing system error condition architecture.

Method and system for use of a field programmable function within an application specific integrated circuit (ASIC) to access internal signals for external observation and control

An application specific integrated circuit (ASIC) is disclosed. The ASIC comprises a standard cell, the standard cell including a plurality of logic functions. The ASIC further includes at least one FPGA interconnect coupled to at least a portion of the logic functions. The FPGA interconnect can be configured to select a particular logic function of the plurality of logic functions. An ASIC in accordance with the present invention allows &ldquo;field selection&rdquo; of functions that are connected to the internal bus(es) and to external I/O. In addition, functional block connections made with internal buses can be significantly wider and faster than buses brought on chip via external chip I/Os. Further, the ASIC reduces cost because selective bus connections can be made internal to the chip, thus eliminating the need for external pins. Finally, the ASIC reduces the cost of the packaged component by allowing the chip to be packaged in a lower pin count package.

Method and system for use of an embedded field programmable gate array interconnect for flexible I/O connectivity

An application specific integrated circuit (ASIC) is disclosed. The ASIC includes a standard cell, the standard cell including a plurality of logic functions. The ASIC also includes an input/output (I/O) configuration function coupled to at least a portion of the logic functions. The ASIC further includes a field programmable gate array (FPGA) function coupled to the I/O configuration function. The FPGA function controls the I/O configuration function based upon a configuration file. A system in accordance with the present invention reduces the cost and time associated with the timing analysis activities during development. An FPGA function within the ASIC is utilized to control the I/O characteristics such as delay, termination and/or slew rate for the I/O pin mapping. Different I/O configurations will be provided by the FPGA function depending on the environment the ASIC is used in. By providing an ASIC that is adaptable to different timing criteria through FPGA programming, the timing analysis performed by the user of the ASIC will be substantially reduced, resulting in a reduction of the development cycle.

Method and system for use of a field programmable function within a chip to enable configurable I/O signal timing characteristics

An integrated circuit comprising a standard cell is disclosed. The standard cell includes a plurality of logic functions; at least a portion of the logic functions requiring initialization. The circuit includes a field programmable gate array (FPGA) cell coupled to the at least a portion of the plurality of logic functions. The at least a portion of the plurality of logic functions are initialized by the FPGA cell. In a method and system in accordance with the present invention, an on-chip Field Programmable Gate Array (FPGA) cell is configured to implement the required application-specific function initializations. The FPGA cell could be wired directly to each of the registers within the functional blocks requiring initialization. These registers would also be wired to the processor bus allowing software access for normal operation after initialization. Access to these registers can be controlled by a simple muxing structure that allows the FPGA to have direct access to the registers when the chip initialization sequence takes place (Chip_Init signal is asserted) and allows the processor bus to have access after initialization is complete (Chip_Init signal is de-asserted).

Method and system for use of a field programmable interconnect within an ASIC for configuring the ASIC

An application specific integrated circuit (ASIC) is disclosed. The ASIC comprises a standard cell. The standard cell includes a plurality of logic functions. The ASIC further includes a field programmable (FP) logic function for coupling the plurality of logic functions together via a plurality of input and output stages. The FP logic function can be programmed for field repair of at least one of the plurality of the logic functions. A method and system in accordance with the present invention utilizes a distributed field programmable logic block in conjunction with standard cells to provide for field repair and improved redundancy. To describe the features of the present invention in more detail, refer now to the following description in conjunction with the accompanying drawings.

Method and system for use of a field programmable function within a standard cell chip for repair of logic circuits

A sensor for measuring changes in mass air flow is described that uses one or more thermoelectric devices, each of which serves both as a heating element and as a differential temperature sensor. The thermoelectric device or devices are sandwiched between two surface plates. The sensor operates the device or devices in constant current or in pulsed current mode. The operation in constant current mode involves passing the current through one thermoelectric device to create a temperature differential between the two surfaces. A second thermoelectric device generates a voltage in response to the differential, the voltage being proportional to the air flow rate. In another embodiment, the device contains a single thermoelectric device that operates in a pulsed mode, first to create a temperature differential using an applied current, and then to measure the voltage. When the voltage reaches zero, the cycle is repeated. The cycle time determines the air flow rate. The pulsed mode procedure can be used first to heat one surface during one cycle and then to heat the other surface during the second cycle.

Thermoelectric air flow sensor

A device that enables a card to be hot-plugged into a socket on a processor-base machine includes a signal bus arbitrator, a signal bus switch, a power bus switch, a cover plate switch, status signals and a controller. The controller monitors the status signals and other signals from the cover plate switch and the signal bus arbitrator to generate control signals that activate the power bus switch and the signal bus switch to control power and signal transmitting facilities at the socket.

Hot plug subsystem for processor based electrical machine

A frame for inserting and/or removing circuit cards from the housing of a machine includes a circuit card carrier connected to a locking CAM slide that is disposed to move within the channel of an actuator bar. A slot with a locking feature is fabricated on the locking CAM slide. A pin extending from a surface of the actuator bar into the channel coacts with the locking mechanism to lock the actuator bar relative to the locking CAM.

Device for inserting circuit cards into electrical machines

Hot plug of adapters using optical switches

The device includes a universal carrier plate with openings for cooling attached circuit boards and openings for coacting with brackets to mount different size circuit boards. A positioning mechanism is connected to the universal carrier plate and rides on tracks in the housing to position the carrier plate and its attached circuit board.

Growing community of inventors

Cary, NC, United States of America

Robert Thomas Bailis