Motorola Corporation

Robert Tapei Yu

Alan Richard Bormann

A random access memory includes a plurality of one-transistor storage cells. A plurality of sense-write conductors are included, each connected to a plurality of storage cells in a row of storage cells. A plurality of regenerative sense amplifiers are each coupled to two sense-write conductors. A one-transistor dummy storage cell is connected to each sense-write conductor. Read-write circuitry is coupled between a data conductor of the memory chip and a storage node of one of the dummy storage cells of each row of storage cells. The dummy storage cell is selected whenever a storage cell on the opposite side of the regenerative sense amplifier is selected. Charge initially stored in the selected storage cell is redistributed on the opposite sense-write conductor and is subsequently amplified by the sense amplifier, and produced in inverted amplified form at the storage node of the dummy storage cell. Capacitive loading on all of the sense-write conductors of the memory chip during redistribution of charge in the selected storage cell is thereby reduced, thereby increasing the magnitude of the sense-write conductor voltage transitions when a storage cell is selected.

Read-write circuitry for one transistor per bit random access memory

A speed-up circuit for a bit sense line of an MOS RAM includes a cross-coupled latch circuit having an output coupled to the bit sense line. When partial discharging of the bit sense line is accomplished through the selected storage cell, the latch circuit switches states and completes discharge of the bit sense line much more rapidly than could have been achieved by the action of the selected storage cell alone. A disabling circuit is connected to the gate of a pull-down MOSFET of the latch circuit connected to the output thereof to turn off the pull-down MOSFET during a write cycle or during the write portion of a read-modify-write cycle. The output of the disabling, or turn-off, circuit operates in response to a signal derived from a clock signal and a chip enable signal applied to the MOS RAM. A bootstrap circuit is provided including a bootstrap charging MOSFET having its gate coupled to V.sub.DD, its source coupled to the bootstrap capacitor, and its drain coupled to a clock signal conductor, to provide low-power dissipation and fast rise time.

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Tempe, AZ, United States of America

Robert Tapei Yu