International Business Machines Corporation

Other

Robert Tamlyn

Nathan R Hiltebeitel

Edward Butler

Steven William Tomashot

Randall L Henderson

Dale E Pontius

Andrew D Bowen

Satish Gupta

Hemen R Shah

Todd Williams

Timothy J Ebbers

Darren Lane Anand

Endre P Thoma

Billy J Knowles

Donald W Price

Yee-Ming Ting

Thomas W Wyckoff

Alfred L Sartwell

Michael A Aranda

Warren W Grunbok

Martin B Lundberg

William R Milani

De Tran

Henry Yeh

Ronald A Sasaki

Douglas R Moran

Pushkar U Mokashi

Robert B Goodwin

The present invention discloses a system and method of testing semiconductor memory devices formed as integrated circuits on semiconductor substrates. The present invention allows parallel testing of arrays using only one input/output (I/O or DQ) to write to the arrays and only two DQs to read from the arrays. The broad search should be directed to methods of compressing the time and number of I/O's required for testing wide, high pin count, or highly partitioned memory arrays. The specific method of this invention comprises simultaneously writing the same test bit to each array, simultaneously reading a common address from each array and comparing the output of each array to report a fail if all outputs are not the same.

Compressed input/output test mode

A postamble corruption protection circuit is provided that disables data latching by a first falling edge register following a data strobe (DQS) falling edge until the data within the first falling edge register has been latched into a second falling edge register in response to a second falling edge register latching signal. Specifically, data latching by the first falling edge register is disabled following each DQS falling edge and is enabled following each second falling edge register latching signal. Data latching of the first falling edge register is controlled by the output of a set/reset register which is gated with the DQS to form a first falling edge register latching signal. When the set/reset register is set, data latching is enabled and when the set/reset register is reset, data latching is disabled. The set/reset register is set in response to a second falling edge register latching signal and is reset in response to a DQS falling edge.

Method and apparatus for preventing postamble corruption within a memory

An invention is disclosed which implements bit line redundancy in a memory module, such as a dynamic random access memory (DRAM), in accordance with a block write operation. The block write operation is commonly used in dual port RAMs, sometimes referred to as video random access memories (VRAM). Specifically, a block write operation allows a plurality of bits of data to be written to a plurality of adjacent bit lines defined by a column address. The precise combination of adjacent bit lines selected by the column address is designated by an address mask. The invention provides a memory module with a redundant bit decoder that incorporates an address masking function into the redundant bit decoder during block write operations and also bypasses a masking function during normal read and write operations. This redundant bit decoder allows a single redundant bit line to replace any single defective bit line of the selected group of block write bit lines. It eliminates the need for replacing all the selected bit lines and, thereby, saves silicon area and maximizes the utilization of available redundant bit elements.

Redundancy architecture and method for block write access cycles

A circuit for detecting an input signal, the circuit having an input node and an output node, includes a first latch having a set input coupled to the input node, for detecting falling transitions at the input node. A second latch having a set input coupled to the input node, detects rising transitions at the input node. A first logic device, responsive to outputs of the first and second latches, detects that an input signal has been received at both the first and second latches. A second logic device, responsive to a complement output of both the first and second latches, resets both the first and second latches.

Non-delay based address transition detector (ATD)

An apparatus and method for enhancing serial access memory (SAM) performance incorporating a pipeline technique that removes a first bit clock cycle latency. In a video DRAM (VDRAM) read operation, accessed VDRAM data is provided simultaneously to the SAM and to a primary latch. The first bit of the VDRAM data is moved from the primary latch to a secondary output port of the memory apparatus ahead of the second through n.sup.th bits of the SAM data.

No latency pipeline

A high performance latch for read and write operations in RAM having a Complimentary Interlock circuit that eliminates the need for external timing to the RAM which might limit its high performance operation. For both read and write operations, the complementary interlock circuit extends a latching signal until valid data appears on the read or write data lines, thus preventing a valid data miss.

High performance extended data out

A multimedia dynamic random-access memory (DRAM) or video random-access memory (VRAM) having enhanced block overwrite capabilities includes a plurality of sense amplifiers which are selectively coupled to an array of memory cells via paired bit lines for sensing/writing charge to the memory cells. Each sense amplifier is controlled by a primary set device and a secondary set device. The secondary set device is of smaller size than the primary set device but still sized sufficiently to maintain accessed data appearing on the paired bit lines. Upon decoding of a block overwrite request, the primary set device is momentarily turned off to facilitate forcible overwriting of selected sense amplifiers with new data while the secondary set device maintains data appearing on unselected sense amplifiers. Once block overwrite is complete, the primary set device is reactivated and charge is restored to the memory cells. By momentarily deactivating the primary set device, block overwriting of a large number of bit line pairs is possible.

Semiconductor memory circuit with block overwrite

A dynamic random access memory (DRAM) device that is selectively operable in a normal write mode, in a block write mode, or in a blocked flash write mode in accordance with a mode select signal. In the preferred embodiment, each column of a 512.times.512 DRAM is divided into eight superblocks of 64 columns, each superblock being in turn divided into eight blocks of 8 columns each. An address decoder decodes the most significant column address bits A8-A6 to provide a group select signal specifying a 64-bit superblock, the next most significant column address bits A5-A3 to provide a block select signal specifying a 8-bit block, and the least significant column address bits A2-A0 to provide a cell select signal specifying a particular column. In the normal write mode, data is written to the specified column in the specified block in the specified superblock. In the block write mode, the same data is simultaneously written to selected columns in the specified block in the specified superblock. In the blocked flash write mode, the same data is simultaneously written to selected blocks in the specified superblock. An 8-bit data input line (D7-D0) is used to provide bits that select columns in the block write mode or blocks in the blocked flash write mode.

Blocked flash write in dynamic RAM devices

A memory system and a unique memory chip is disclosed wherein multiple islands on a chip can be separately accessed by separate island controllers whereby concurrent use of the several islands or arrays on a chip can be achieved.

Memory system and unique memory chip allowing island interlace

The selection in a dual port memory device of data from a serial access memory register having a lower byte and an upper byte of data is described herein. In one embodiment, the register is partitioned lengthwise into two sections, corresponding to, for example, a frame buffer A and a frame buffer B. On each serial clock cycle, frame buffer A or frame buffer B for each byte of data may be selected from the register. Each of the selected bytes of data are then passed to a serial output port. In another embodiment, the lower byte of data corresponds to, for example, a frame buffer A and the upper byte corresponds to a frame buffer B. Then either the upper byte or lower byte of data is selected to be output on the serial port. In yet a further embodiment, the serial access memory register is partitioned lengthwise into two sections, each section corresponding to, for example, a frame buffer and the bytes of data correspond to another buffer, then either the lower byte or upper byte is selected to be output on the serial port.

SAM data selection on dual-ported DRAM devices

An implementation of a serial access memory register that facilitates the selecting from two alternate frame buffers on a per pixel basis. The frame buffers are each stored in a portion of a row in a single video RAM. Following data transfer to the serial access memory register, data from each of the two frame buffers is available. A double buffer select signal controls the selection of which half of the serial access memory register will put data on the output bus for each serial clock signal. The serial clock increments the address pointers in both halves of the serial access memory port simultaneously.

Video RAM double buffer select control

An implementation of a serial access memory register facility which allows the external selection of the portion of the SAM to be scanned out. A control signal is provided which causes the reloading of serial access memory address counter causing the reloading of serial access memory address counter causing the serial scanning to shift from one to another of the serial access memory registers. The result is an ability to select a stopping point when scanning out of the serial access memory. Thus, the present invention implements the ability in a video random access memory to specify both the starting and ending points of the data to be scanned out of the serial access memory. The preferred embodiment replaces the QSF status pin with a control pin to preserve the packaging configuration of standard VRAMs.

Video ram with external select of active serial access register

A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells. A first set of mux devices selects one of the two pairs of folded bit lines from each of the arrays, and a second set of mux devices selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

Growing community of inventors

Jericho, VT, United States of America

Robert Tamlyn