Other

Harris Corporation

General Electric Company

Infineon Technologies Ag

Intersil Americas Inc.

Qimonda Ag

Intersil Corporation

Infineon Technologies Richmond, LP

Robert T Fuller

Robert Sanders

Robert K Lowry

Michael Rennie

David A Decrosta

Heinrich Ollendorf

Michael J Morrison

Stacey Cabral

Howard L Evans

Joseph C Tsang

David Pasek

Helmut Schneider

Michael D Church

Mario Ghezzo

John T Gasner

Chris A McCarty

William R Richards, Jr

Frank Prein

Richard I Proctor

Jonathan Philip Davis

Rodger G Parent

Jon Davis

Franz Hagl

Metal residue on a semiconductor surface resulting from metal chemical mechanical polishing ('CMP') process are eradicated using a dry clean process. The dry cleaning uniformly removes or substantially eliminates metal residue from the surface of the semiconductor. An unintended metal short that may be present due to the residue may thereby be eliminated by adjusting the dry cleaning process based on a type of dry cleaning material, and type and a thickness of the residue.

Post metal chemical mechanical polishing dry cleaning

An edge protection process for semiconductor device fabrication includes forming a protective layer on the circumferential edge region of a semiconductor substrate. The semiconductor substrate is placed in a plasma atmosphere and trench structures, such as deep trenches and shallow trench isolation structures are etched in the substrate. The protective layer substantially prevents the etching of the circumferential edge region, such that the formation of black silicon is substantially minimized during the etching process.

Edge protection process for semiconductor device fabrication

An integrated semiconductor circuit, in particular a semiconductor memory circuit, having at least one integrated electrical antifuse structure is described. The antifuse structure is located within an insulated well composed of semiconductor material.

Integrated semiconductor circuit, in particular a semiconductor memory circuit, having at least one integrated electrical antifuse structure, and a method of producing the structure

A friction pad to be used in conjunction with a cartridge in a caulking (or any cartridge type) dispenser. The invention contemplates using the friction pad in conjunction with an existing caulking dispenser to prevent the rotation of the cartridge by simply placing the friction pad in the front end of the dispenser. In its most basic embodiment, the present invention contemplates a friction pad adapted to be fitted between a front face of a cartridge type dispenser and a cartridge to prevent rotation of the cartridge, the friction pad comprises: a front face adapted to be fitted in engagement with front end of the dispenser; and a back face adapted to be fitted in engagement with the cartridge.

Retrofit friction pad for fluid material dispenser

To program a CMOS memory, an auxiliary bipolar transistor is formed in a P-well adjacent to the P-well of an NMOS device of the CMOS memory, the auxiliary transistor being capable of forcing a large magnitude current through a fusible link, so as to program the electronic state of the CMOS memory cell into a prescribed binary (1/0) condition. A separate implant mask for the emitter region of the auxiliary transistor allows the geometry and impurity concentration profile of the emitter region to be tailored by a deep dual implant, so that the impurity concentration of the emitter region is not decreased, and yields a reduced base width for the auxiliary transistor to provide a relatively large current gain to blow the fuse, while allowing the doping parameters of the source/drain regions of the CMOS structure to be separately established to prevent thyristor latch-up.

CMOS integrated circuit architecture incorporating deep implanted emitter region to form auxiliary bipolar transistor

A manufacturing process for producing dynamic random access memories (DRAMs) having redundant components includes steps for concurrently forming normal (i.e. non-fused) contacts to components of the DRAMs and anti-fused contacts to the redundant components. The process by which the normal and anti-fused contacts are made is readily implemented using standard integrated circuit processing techniques. An anti-fuse contact ( ) and a normal (i.e. non-fused) contact ( ) are formed by opening respective contact areas in a dielectric ( ), selectively forming an insulating layer ( ) over the anti-fuse contact, applying polysilicon ( ) to cover the insulating layer of the anti-fuse contact and to fill the opening over the normal contact. In one embodiment of the invention, the circuit region served by the anti-fuse contact is subject to ion implantation ( ) to improve its conductivity before the anti-fuse contact is formed. In another embodiment of the invention, the anti-fuse is formed in an isolated well ( ) on the integrated circuit device and a non-fused contact ( ) to the well is also provided to aid in blowing the anti-fuse.

Method for making an anti-fuse

A method for rounding corners of a silicon substrate, in accordance with the present invention, includes forming a plateau on a silicon substrate having corners at edges of the plateau. A mask is formed on a top surface of the plateau, which is recessed back from vertical edges of the plateau to provide exposed horizontal portions. Fluorine or Argon dopants are implanted at the corners and on the exposed portions, and the substrate is oxidized such that the corners become rounded providing a gradual transition at the edges of the plateau.

Silicon corner rounding by ion implantation for shallow trench isolation

A EEPROM 140 has a storage transistor 160 with a gate insulating layer 104 of BPSG and a polysilicon gate 112.2 of the same layer as the polysilicon gate 112.1 of the FET transistor 150. The BPSG layer 104 has POHC traps that capture holes injected into N well 103.2. A positive voltage applied to N well 103.2 programs the storage transistor 160 off. Applying a positive voltage to the gate 112.2 neutralizes the holes stored in layer 104 and erases the memory of transistor 160.

Radiation hardened dielectric for EEPROM

An integrated circuit includes a plurality of CMOS transistors formed in a monocrystalline substrate. Within the substrate is a plurality of complementary spaced pairs of a p-well region and a n-well region. Between each well region, each of which has a source, gate, and drain, is a self-aligned trench filled with semiconductor material. A method of fabricating a field effect transistor entails a first step of forming a layer of first insulative material over a monocrystalline substrate. Next, a layer of semiconductor material is formed over the first insulative material. A p- or n-well masking layer is formed over the semiconductor layer and patterned to expose a first portion of the underlying semiconductor layer. A first dopant of one polarity is implanted in the region of the substrate aligned with the semiconductor layer first portion, which is then converted into a second insulative material. The masking layer is removed, thereby exposing the remaining portion of the semiconductor layer. A second dopant of opposite polarity to the first dopant is then implanted into the remaining portion. Removal of the first portion and the exposed remaining portion of the semiconductor material exposes a step of semiconductor material, which, along with a portion of the substrate aligned with the step, is subsequently removed to form a trench. The trench is filled with a second semiconductor material.

Method for forming complementary wells and self-aligned trench with a

The present invention is directed to a silicon carbide field effect transistor. The FET is formed on a silicon carbide monocrystalline substrate. An insulative material gate having a pair of spaced apart sidewalls is patterned on the substrate. The insulative material comprises a first insulation material overlayed by an electrically conductive layer. Within the substrate is lightly doped base regions located partially under the sidewalls of the gate and extending into the exposed substrate. Associated with the lightly doped base regions are heavily doped source regions aligned with the exposed substrate. On the underside of the substrate is a drain region to form the FET. Further in accordance with the present invention, a method to fabricate a field effect transistor is disclosed. The transistor is formed in a monocrystalline substrate of silicon carbide. Forming a transistor on the silicon carbide substrate entails depositing a first electrically insulative layer over the substrate. Next, an electrically conductive layer is deposited over the first insulative layer and then a second electrically insulative layer is deposited over the conductive layer. The following step includes partially removing the second insulative layer and exposing a portion of the first conductive layer to obtain two spaced apart regions of the silicon carbide substrate for forming lightly doped base regions. Then the substrate aligned with the exposed portion of the first conductive layer is lightly implanted with a dopant to form lightly doped base regions. Next, a layer of a third insulative material is formed on the sidewalls of the second insulative material. The following step entails removing the exposed conductive layer not aligned with the second insulative material and third insulative material. Thereby, exposing portions of the first insulating layer and defining a second set of spaced regions of the substrate. The second set of spaced regions are then heavily implanted to form heavily doped source regions. The second insulative material and third insulative material are then removed to form a gate.

Self-aligned power field effect transistor in silicon carbide

The present invention is directed to a process for forming a self-aligned raised source/drain MOS device comprising a planarized metal layer, preferably tungsten, overlying a source, a drain, and a gate that is provided on both sides with an insulating spacer to electrically isolate it from the source and drain. The planarized tungsten layer comprises a first portion whose lower surface is in contact with a polysilicon layer of the gate. The lower surface of each of the second and third portions of the tungsten layer is in contact with the source and drain, respectively. The second and third portions are insulated from the first portion by the insulating spacers, and the upper surfaces of all the portions comprise a coplanar surface. Planarization of the deposited metal layer thus provides ohmic contact at substantially the same level to the source, drain, and gate. In a self-aligned raised source/drain MOS device formed by the process of the invention, the second and third portions of the planarized metal layer preferably extend laterally over the field oxide and are characterized by an upper:lower surface width ratio of from about 2:1 to 4:1.

Process for forming a self-aligned raised source/drain MOS device and

A radiation hardening isolation technique uses a poly buffered LOCOS structure (34, 36) to protect the device areas during field oxide 40 formation. The field oxide 40 is removed, and the polysilicon structure 34 is covered with a PSG or BPSG layer 42. Layer 42 is planarized and the polysilicon 34 is removed to provide a self-aligned device region 31.

Method and apparatus for radiation hardened isolation

Frozen food is thawed automatically by disposing the food within a container having a trough disposed adjacent to a top of the container, the trough being connected to a drain, filling the container with water to a predetermined level, providing a controlled metered secondary flow of fresh water into the container so as to cause the water level to rise and flow into the trough, forcibly recirculating, using a pump, water in the container so as to produce sufficient water circulation to maintain a substantially even water temperature distribution therein and so as to produce sufficient agitation of the water to break loose small food particles from the frozen food immersed in the water such that the food particles and food-related oils and debris float to the surface of the water and are carried into the trough.

Growing community of inventors

Melbourne Beach, FL, United States of America

Robert T Fuller