Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Robert Streitenberger

Hiroyuki Kawai

Yoshitsugu Inoue

Junko Kobara

Keijiro Yoshimatsu

Hiroyasu Negishi

Hiroyuki Morinaka

Nelson Chan

The method of routing configuration accesses applied from the primary port to a plurality of secondary ports includes the steps of: distributing a plurality of configuration accesses received from the primary bus to the plurality of secondary ports in accordance with a predetermined algorithm, such that each of the devices on the secondary ports receives and responds to exactly a single access; and terminating configuration cycles after distributing the plurality of configuration accesses.

Method and apparatus for routing configuration accesses from a primary port to a plurality of secondary ports

A square root extraction circuit and a floating-point square root extraction device which simplify a circuit structure and improve an operation speed are provided. Portions for generating square root partial data (q to q ) include carry output prediction circuits ( to ), respectively. The carry output prediction circuit (i) (i equals any one of 3 to 8) receives condition flags (AHin, ALin), the most significant addition result (SUM), and square root partial data (q(i&minus;1)) from the preceding square root partial data generating portion, and also receives a carry input (Cin) to output condition flags (AHout, ALout) for the next square root partial data generating portion, and square root partial data (q(i)). The condition flags (AHout, ALout) serve as the condition flags (AHin, ALin) for the carry output prediction circuit (i&plus;1), respectively.

Square root extraction circuit and floating-point square root extraction device

A graphic processor includes first and second buses and a plurality of geometric operation units having an output connected to the second bus, and a circuit to allocate a plurality of ordered data blocks formed of data to be operated upon to the plurality of geometric operation units, and an input of at least one of the plurality of geometric operation units is connected to the first bus. The plurality of geometric operation units include all arbitrating circuit to arbitrate the order of output between an output buffer to store a result of processing by the allocated data blocks and another geometric operation unit, and output data resulting from processing onto the second bus in an order corresponding to the sequence of the plurality of data blocks of data to be operated upon.

Graphic processor having multiple geometric operation units and method of processing data thereby

A logarithmic arithmetic unit includes first logarithmic operation part multiplying an exponent part of floating-point data by a prescribed value, a logarithmic table memory outputting a logarithmic value corresponding to bit data expressing a digit higher than a prescribed digit of a fixed-point part of the floating-point data, divisional precision decision part deciding divisional precision on the basis of the exponent part, division part performing division on a dividend obtained by subtracting the bit data from the fixed-point part and a divisor of the bit data and obtaining a result of division of a number of digits set on the basis of the divisional precision, second logarithmic operation part obtaining the logarithmic value of a value obtained by dividing the fixed-point part by the bit data and sum operation part adding outputs from the first and second logarithmic operation parts and the logarithmic table memory to each other.

Logarithmic arithmetic unit avoiding division as far as predetermined arithmetic precision is guaranteed

An FIFO data transfer control device includes an instruction analyzing portion for analyzing an instruction for data transfer to an FIFO storage device including a plurality of banks, and calculating an amount of data to be transferred; a data count portion for calculating, from the data amount calculated by the instruction analyzing portion, an amount of the data written in the bank being in an outputting state, and issuing a determination flag indicating whether the free space of the bank being in the outputting state satisfies predetermined conditions or not; and a full check portion for inhibiting processing of a next instruction until the determination flag sent from the data count portion or the full flag issued from the FIFO storage device is reset.

First-in first-out data transfer control device having a plurality of banks

A bridge includes a first port connected to a Primary bus, and second ports respectively connected to second buses. The first port includes a PCI master, a PCI slave and an AGP master. Each of the second ports includes a PCI master, a PCI target and an AGP Target. The bridge further includes a plurality of first-in-first-out memories forming asynchronous data paths between the first port and the second ports and arbitrators for arbitrating a contention between the transactions on the data paths formed by the first-in-first-out memories based on the protocols related to the transactions.

Bridge device for connecting multiple devices to one slot

The geometry processor includes mutually independent first and second external interface ports connected to a host processor, and a rendering processor, respectively, and a geometry calculation core which processes a geometry calculation applied through the first external interface port from the host processor. The geometry calculation core includes a plurality of SIMD type floating point calculating units, a floating point power computing unit, an integer calculating unit, a controller responsive to an instruction from the host processor which controls the plurality of floating point calculating units, the floating point power computing unit and the integer calculating unit to process data from the host processor, and an output controller which outputs the processed data to the rendering processor through the second external interface port.

Geometry processor capable of executing input/output and high speed geometry calculation processing in parallel

In a floating point adder adding received two floating point data together and subtracting one such data from the other, before their exponent parts are matched in digit by a digit match unit the two data have their exponent parts compared and also their fraction parts compared, and a result of each comparison and a sign of each data are used to code a relationship in magnitude between data corresponding to a clipping coordinate and the other data fed. A clip code generated depending on the previously obtained comparison results from exponent part and fraction part compare units, rather than depending on a zero flag according to a result of an addition or a subtraction and a sign of the result of the addition or the subtraction, can rapidly be generated without the circuit increased in scale.

Floating point adder capable of rapid clip-code generation

A power operation device comprises a bit operation unit or performing a bit shift operation on a logarithmic base bit string from a logarithm operation unit according to an input exponent bit string Y, and for furnishing the shifted logarithmic base bit string as a multiplication bit string. An exponent checking unit checks whether or not the input exponent bit string Y is the i power of a base 2 where i is an integer, and, if so, furnishes a selection signal to direct selection of the multiplication bit string from the bit operation unit. A multiplication bit string selection unit selects and furnishes the multiplication bit string when it receives the selection signal from the exponent checking unit. In contrast, the multiplication bit string selection unit selects and furnishes another multiplication bit string from a multiplier otherwise. An exponential operation unit performs a base-2 exponential operation on the selected multiplication bit string from the multiplication bit string selection unit, i.e., computes 2 where Z is the selected multiplication bit string, and furnishes the computed base-2 exponential value as the power operation-result X .

Power operation device

An output FIFO data transfer control device can comprise a geometric arithmetic core including one integer processing unit or IPU and a plurality of floating-point processing units or FPUs. Each processing unit includes an intermediate buffer or data output buffer for storing a data on an arithmetic result. When an instruction of data transfer from at least one of the plurality of processing units to one output FIFO is issued, a write/read pointer generating unit generates a write pointer identifying a specific location where data on an arithmetic result associated with the instruction is to be stored in the intermediate buffer of at least one of the plurality of processing units. The write/read pointer generating unit also generates a read pointer identifying a specific location where data is to be read out of the intermediate buffer of at least one of the plurality of processing units. A transfer mode setting unit sets a transfer mode identifying which at least one of the plurality of processing units is to transfer data on an arithmetic result, and sequentially furnishes a read enable signal to at least one of the plurality of processing units so as to read out the data from the intermediate buffer of at least one of the plurality of processing units.

Output FIFO data transfer control device

A PCI-PCI bridge is connected between a primary PCI bus and a secondary PCI bus, and includes a bridge for connecting the secondary PCI bus to the primary PCI bus. The bridge has a type &ldquo;00&rdquo; configuration header, and identifies, at the time of configuration, one of a plurality of PCI agents including a VGA device on the secondary PCI bus based on a value of a function number field of the configuration command from the device driver, and that the identified agent to execute configuration.

PCI-PCI bridge allowing controlling of a plurality of PCI agents including a VGA device

A square root extraction circuit and a floating-point square root extraction device which simplify a circuit structure and improve an operation speed are provided. Portions for generating square root partial data (q3 to q8) include carry output prediction circuits (3 to 8), respectively. The carry output prediction circuit (i) (i equals any one of 3 to 8) receives condition flags (AHin, ALin), the most significant addition result (SUM), and square root partial data (q(i-1)) from the preceding square root partial data generating portion, and also receives a carry input (Cin) to output condition flags (AHout, ALout) for the next square root partial data generating portion, and square root partial data (q(i)). The condition flags (AHout, ALout) serve as the condition flags (AHin, ALin) for the carry output prediction circuit (i+1), respectively.

Square root extraction circuit and floating-point square root extraction

Three local buses and three composite operation buses are provided in each processing element. An arithmetic logic unit, a multiplier, a bit operator, and an accumulator are connected to respective local buses and the composite operation buses. As a result, each operation unit can transfer data efficiently using a plurality of buses of different functions.

SIMD processor operating with a plurality of parallel processing

There is disclosed a high-speed programmable image processing LSI circuit adaptable to image preprocessing, feature extraction, and matching, which includes a DMA transfer control portion (4) for DMA transfer which reads input data from an external memory to transfer the input data to data memories in the LSI circuit; a sequence control portion (8), an instruction memory (7), and an address generating portion (3) which control writing to and reading from the data memories in response to an instruction code; the DMA transfer control portion (4) accommodating a wait time caused during external data transfer to prevent the wait time from affecting instruction code control in the LSI circuit; SIMD type processing units arranged in parallel and connected to output lines of the data memories for completing the process steps of image processing in cooperation with a postprocessing portion which in turn provides an output signal (54) to the exterior and accommodates a wait time at this time.

Image processing LSI circuit with image preprocessing, feature

The present invention is directed to a program control unit which enables a program control to achieve an efficient loop processing which does not immediately follow a loop instruction and which contains a start address and end address. In the program control unit, the start address and end address of a loop processing are stored in a register (start) (7) and a register (end) (8), respectively, in synchronization with a clock t1. The stored data 'start' of the register (7) and the stored data 'end' of the register (8) are inputted to a comparator (12) and a comparator (11), respectively. The comparator (12) compares the output from a delay program counter (18) with the data 'start', and sets a flag f start when the comparison result indicates agreement and otherwise resets it. The comparator (11) compares the output from a delay program counter (18) with the data 'end', and sets a flag f end when the comparison result indicates agreement and otherwise resets it.

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Hyogo, Japan

Robert Streitenberger