Texas Instruments Corporation

Robert Steinhoff

Jonathan S Brodsky

Thomas A Vrotsos

Sameer P Pendharkar

David John Baldwin

Timothy Patrick Pauletti

Wayne Tien-Feng Chen

Charvaka Duvvury

Philip Leland Hower

Joseph A Devore

John Eric Kunz, Jr

Sameer Pendharker

An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.

Bi-directional ESD protection circuit

A structure is designed with an external terminal () and a reference terminal (). A first transistor () is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor () has a current path coupled between the external terminal and the substrate. A third transistor () has a current path coupled between the substrate and the reference terminal.

Bi-directional electrostatic discharge (ESD) protection circuit

The present invention relates to electrostatic discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more fingers of an ESD protection device so that the ends of the fingers have a reduced initial trigger or breakdown voltage as compared to other portions of the fingers, and in particular to central portions of the fingers. In this manner, most, if not all, of the adjusted ends of the fingers are likely to trigger or fire before any of the respective fingers completely enters a snapback region and begins to conduct ESD current. Consequently, the ESD current is more likely to be distributed among all or substantially all of the plurality of fingers rather than be concentrated within one or merely a few fingers. As a result, potential harm to the ESD protection device (e.g., from current crowding) is mitigated and the effectiveness of the device is improved.

Reduced finger end MOSFET breakdown voltage (BV) for electrostatic discharge (ESD) protection

An apparatus for reducing current leakage between an input locus and at least one power rail for a system includes, for each respective power rail: (a) A first diode unit coupled between the input locus and a coupling locus. The first diode unit is configured to effect substantially zero potential drop during normal operation of the apparatus. (b) A second diode unit coupled between the coupling locus and the respective power rail. The second diode unit is configured to present no forward bias during normal operation of the apparatus. The first and second diode units cooperate to effect current flow between the input locus and the respective power rail during a predetermined operational condition of the apparatus.

Apparatus and method for reducing leakage between an input terminal and power rail

Methods and circuits are disclosed for protecting an electronic circuit from ESD damage using an SCR ESD cell. An SCR circuit is coupled to a terminal of an associated microelectronic circuit for which ESD protection is desired. The SCR used in the ESD cell of the invention is provided with a full guardring for shielding the SCR from triggering by fast transients. A resistor is provided at the guardring for use in triggering the SCR at the onset of an ESD event. Exemplary preferred embodiments of the invention are disclosed with silicide-block resistors within the range of about 2-1000 Ohms or less.

Method of making and using guardringed SCR ESD protection cell

Guardringed SCR ESD protection

An ESD protection device can include a silicon-controlled rectifier (SCR) and an external pumping circuit. The external pumping circuit can be used to forward bias a junction of the SCR. The external pumping circuit can comprise a transistor that can be coupled to a region of the SCR to pump the region.

Pumped SCR for ESD protection

The present invention provides a system for electrostatic discharge protection in a semiconductor device, utilizing a silicon-controlled rectifier (). The system includes the silicon controlled rectifier, which has a first p-type region () coupled to a voltage node (), a first n-type region () having a first side adjoining the first p-type region, a second p-type region () having a first side adjoining a second side of the first n-type region, and a second n-type region () having a first side adjoining a second side of the second p-type region. A clamping structure () is intercoupled between the second n-type region and ground, to prevent the junction between the second p-type region and the second n-type region from retaining a forward bias. A switching structure () is intercoupled between the second p-type region and ground to ground the second p-type region during normal operation of the semiconductor device.

Versatile system for electrostatic discharge protection utilizing silicon controlled rectifier

The present invention relates to electro static discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more fingers of an ESD protection device so that the ends of the fingers have a reduced initial trigger or breakdown voltage as compared to other portions of the fingers, and in particular to central portions of the fingers. In this manner, most, if not all, of the adjusted ends of the fingers are likely to trigger or fire before any of the respective fingers completely enter a snapback region and begin to conduct ESD current. Consequently, the ESD current is more likely to be distributed among all or substantially all of the plurality of fingers rather than be concentrated within one or merely a few fingers. As a result, potential harm to the ESD protection device (e.g., from current crowding) is mitigated and the effectiveness of the device is improved.

The present invention includes a MOS device () that has a P-type substrate () and an N-type drain region () formed within the substrate (). An annular N-type source region () generally surrounds the drain region (). The source region () serves as both the source for the MOS device () and a sacrificial collector guard ring for an electrostatic discharge protection circuit. An annular gate region () generally surrounds the drain region () and is electrically insulated from the drain region () and electrically connected to the source region (). An annular P-type bulk region () generally surrounds the source region () and is electrically connected to the source region ().

MOS ESD CDM clamp with integral substrate injection guardring and method for fabrication

An equipment () for testing semiconductor device performance under high energy pulse conditions, which comprises a high voltage generator () and an on/off switch relay (). The relay is resistively connected by a first resistor () to the generator and by a second resistor () to the socket () for the device-under-test (); the relay is operable in a partially ionized ambient. A capacitor () is connected to the relay, to the generator, and to the device, and is operable to discharge high energy pulses through the device. A third resistor () is in parallel with the capacitor and the device, and is operable to suppress spurious pulses generated by the relay. This third resistor has a value between about 1 k&#x3a9; and 1 M&#x3a9;, preferably about 10 k&#x3a9;, several orders of magnitude greater than the on-resistance of the device-under-test.

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Dallas, TX, United States of America

Robert Steinhoff