International Business Machines Corporation

Robert Spencer Horton

Clarence Rosser Ogilvie

Paul Mark Schanely

David W Milton

Bill N On

Tad Jeffrey Wilder

Robert Dov Herzl

Kenneth Anthony Lauricella

Charles B Winn

Nitin Sharma

Robert Michael Dinkjian

Michael Y Lee

Charles S Woodruff

Chandrasekhar Narayanaswami

Eric Oliver Mejdrich

Giora Biran

Jamie Randall Kuesel

Bengt-Olaf Schneider

Robert Allen Drehmel

Andrew D Bowen

James Lewis Van Welzen

David C Tannenbaum

Mark E Kautzman

Ming-i Mark Lin

Mark Christopher Fowler

Kirk Steffen Haskell

Huu N Dinh

Mark Van Horn

Sebastian Theodore Ventrone

Robert J Devins

Thomas Y Kwok

Thomas Yu-Kiu Kwok

Douglas P Nadeau

Jorge Gonzalez-Lopez

Steve Mastrianni

Thomas P Lanzoni

Leland D Richardson

William L Luken, Jr

Ralph C Mitchell

Walter G Temnycky

A controller sets a selector register of programmable delay signal logic is to a value equal to a required number of clock cycles of delay for signals output from an integrated circuit to an external memory. The controller controls a selection of additional logic along the output path to perform on the delayed signal within a clock cycle without any latency added to the output path by delay signal logic outputting the delayed signal. The controller waits required number of clock cycles after setting the selector register before using the delayed signal output by the delay signal logic onto an output path.

Distributing multiplexing logic to remove multiplexor latency on the output path for variable clock cycle, delayed signals

Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.

Managing out-of-order memory command execution from multiple queues while maintaining data coherency

A logic unit is configured with least one multiplexor distributed along a delay path of a logic unit, wherein each at least one multiplexor is configured to receive two inputs and output one of the two inputs, wherein each at least one multiplexor is configured to select one of the two inputs to control a particular programmable number of clock cycles of delay added to a signal from 1 to N clock cycles. The logic unit is configured with at least two latches distributed along the delay path of the logic unit, wherein each at least one latch is configured to add a clock cycle of delay, wherein a terminating latch from among the at least two latches is configured to output the signal delayed by the particular programmable number of clock cycles.

A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures. The second semiconductor device comprises the additional structure layer located within the second insertion point location.

Semiconductor layer forming method and structure

A chip design methodology. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB).

Method for identifying and implementing flexible logic block logic for easy engineering changes

A design structure for identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.

Structure for identifying and implementing flexible logic block logic for easy engineering changes

A method is provided for updating an existing netlist to reflect a design change. A register transfer level (RTL) design incorporating the design change and the existing netlist are provided to a synthesis tool. The existing netlist is set to a read-only condition to prevent a change to the existing netlist. The design and the read-only existing netlist are processed with the synthesis tool reusing logic structures from the read-only existing netlist by performing an optimization of the design and the read-only existing netlist with an objective to minimize the design space. The optimization is constrained by the read-only existing netlist. A result is generated by the synthesis tool including the existing netlist and a new portion of a netlist reflecting the design change.

Minimizing impact of design changes for integrated circuit designs

A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module.

Computer system bus bridge

A design structure embodied in a machine-readable medium is disclosed in one embodiment of the invention as including a flexible logic block to facilitate engineering changes at selected locations within an IC. The flexible logic block has a consistent and identifiable structure such that a simple automated process may be used to reconfigure the structure to perform different logical operations. In certain embodiments, the flexible logic block includes a circuit, such as a multiplexer, having multiple inputs and at least one output. A metal interconnect structure is coupled to the inputs and enables connection of each of the inputs to one of several electrical potentials using a focused-ion-beam (FIB) tool. In this way, the circuit may be configured to perform different logical operations after components in the IC exist in hardware.

Design structure for facilitating engineering changes in integrated circuits

A method for bridging between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a method for bridging between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI).

A bus bridge for coupling between a first bus and a second includes: at least one data buffer; data load logic and data unload logic. The data load logic places received data in the at least one data buffer, wherein the data is received at the bus bridge from across the first bus in a first data ordering. The data unload logic automatically translates the received data from the first data ordering to a second data ordering during unloading of the data from the at least one data buffer for transfer across the second bus, wherein the first data ordering and the second data ordering are each a different one of a linear data ordering and an interleaved data ordering.

Data ordering translation between linear and interleaved domains at a bus interface

The invention transmits data on an integrated circuit chip by first propagating a first data portion along a first segment of a segmented data line and then propagating the first data portion along a second segment of the segmented data line and simultaneously propagating a second data portion along the first segment of the segmented data line. The invention breaks a single data transmission into such different data portions and later reassembles the different data portions back into the single data transmission after all of the different data portions have been individually transmitted along all portions of the segmented data line

Circuit and method for pipelined insertion

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Colchester, VT, United States of America

Robert Spencer Horton