Freescale Semiconductor,inc.

Nxp Usa, Inc.

Robert Scott Ruth

James W Miller

Melanie Etherton

Mohamed S Moosa

Alex P Gerdemann

Michael A Stockinger

Juxiang Ren

Jonathan M Phillippe

Stefano Pietri

Chris C Dao

Bernard J Pappert

Xavier Hours

Mark A Kearney

Jeff L Warner

Emmanuel U Onyegam

Matthew Clay Lauderdale

Shitiz Arora

Alexey Gilgur

An electrostatic discharge measuring device includes an integrated circuit including a collector, a discharge pad and an ESD detector circuit coupled to the collector and discharge pad. The ESD detector circuit includes a device that detects occurrence and magnitude of an electrostatic discharge between the collector and the discharge pad. In one embodiment, the device is a metal-oxide-semiconductor capacitor. In another embodiment, the device is a thin film storage bitcell. In one embodiment, the electrostatic discharge measuring device is contained in a test microelectronic package. A method includes running the test microelectronic package through a manufacturing process to determine location during manufacturing at which an electrostatic discharge occurs when an externally-similar production microelectronic packages is run through the same manufacturing process.

Electrostatic discharge measuring device

A substrate bias circuit and method for biasing a substrate are provided. A substrate bias circuit includes a first voltage source, a second voltage source, a diode coupled between the first voltage source and the second voltage source, and a plurality of transistors, each transistor in the plurality of transistors having a substrate terminal. In one example, the first voltage source supplies, via the diode, the substrate terminal of a first transistor of the plurality of transistors during a power-up, and the second voltage source supplies the substrate terminal of the first transistor after the power-up.

Substrate bias circuit and method for biasing a substrate

An integrated circuit including ESD circuitry that is shared among more than one terminal segment of the integrated circuit to discharge current from an ESD event on any of the terminal segments. The shared ESD circuitry includes a clamp circuit that is coupled to power buses of each segment to discharge current from ESD events on each segment. The shared ESD circuitry includes a trigger circuit that is coupled to nodes coupled to terminals of each segment to detect an ESD event on each segment.

Shared ESD circuitry

An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.

Electrostatic discharge protection system

A method of performing layout verification for an integrated circuit (IC) layout is described. The method comprises receiving layout information for the IC layout, identifying at least one IC component within the IC layout, extracting localized layout information for the at least one IC component from the received layout information, defining the localized layout information for the at least one IC component within at least one component instance parameter therefor, and performing at least one layout verification check for the at least one component based at least partly on the at least one component instance parameter.

Method and apparatus for performing integrated circuit layout verification

Boosted Electrostatic Discharge (ESD) clamp circuit with high effective holding voltage. In some embodiments, an integrated circuit may include a trigger circuit operably coupled to a first voltage bus and to a reference bus; a diode including an anode terminal operably coupled to a second voltage bus, the second voltage bus distinct from the first voltage bus; a transistor including a gate operably coupled to an output terminal of the trigger circuit, a drain operably coupled to a cathode terminal of the diode, and a source operably coupled to the reference bus; and an input/output (I/O) cell operably coupled to the first voltage bus, the second voltage bus, and the reference bus.

Electrostatic discharge (ESD) clamp circuit with high effective holding voltage

An integrated circuit including an ESD network including a portion located in ESD subareas of a plurality of I/O cells where the ESD subareas are arranged in a row traversing the plurality of I/O cells. The ESD network includes ESD clamp cells and ESD trigger circuit cells wherein a portion of the network is located in the row. In some examples, the row includes an ESD trigger circuit cell with a portion in one subarea of one ESD subarea of one I/O cell and a second portion in a second ESD subarea of another I/O cell. Also described herein is a method for producing an integrated circuit layout with an ESD network.

I/O cell ESD system

A semiconductor device includes CMP dummy tiles () that are converted to active tiles by forming well regions () at a top surface of the dummy tiles, forming silicide () on top of the well regions, and forming a metal interconnect structure () in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.

Growing community of inventors

Austin, TX, United States of America

Robert Scott Ruth