Adtran Gmbh

Robert Scott Appleton

David Bernard Etzkorn

Andrew L Plankenhorn

Steven Creg Killen

Patrick Steven Grant

Paul E Calvert

A test apparatus for telecommunication equipment includes motherboard that executes a resident operation control mechanism, so that the test apparatus exhibits default hardware functionality. However, if a daughtercard has been plugged into the motherboard, the motherboard ignores the default firmware and executes whatever replacement operation control software is provided on the daughtercard&#x2014;causing the test apparatus to acquire a hardware functionality exclusive of the motherboard default.

Daughtercard-based system software and hardware functionality-defining mechanism

A bit error rate test (BERT) system is configured as a field programmable gate array that emulates multiple independent BERT generators. The BERT generators produce test frames containing test pattern codes associated with respectively different time division multiplexed (TDM) digital communication channels, that are not necessarily mutually contiguous within a plurality of TDM timeslots of a network communication frame serving digital communication circuits. A framing unit assembles the test code patterns into a test frame and transmits the test frame over a serial network interface to a plurality of digital channel units of a channel bank. The framing unit also interfaces contents of test code patterns within test frames returned from the channel units over the serial network interface with a plurality of data channel-specific virtual BERT receivers, associated with respective digital communication channels. A bit error processor determines errors in the contents of the test code patterns within returned test frames.

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Madison, AL, United States of America

Robert Scott Appleton