Northrop Grumman Systems Corporation

Northrop Grumnian Systems Corporation

Robert Samuel Howell

Eric Jonathan Stewart

Matthew Russell King

Justin Andrew Parke

Harlan Carl Cramer

Howell George Henry

Bettina A Nechay

Karen Marie Renaldo

Garrett A Storaska

Ronald G Freitag

Shalini Gupta

Harvey C Nathanson

Josephine B Chang

Ken Alfred Nagamatsu

Robert Miles Young

Patrick Bruckner Shea

Marc Eisenzweig Sherwin

Joseph Terence Smith

Monica P Lilly

Wayne Stephen Miller

Pavel Borodulin

James T Kelliher

Matthew J Walker

Nabil Abdel-Meguid El-Hinnawy

William J Sweet

Michael Edward Aumer

Francis W Hopwood

Rowland C Clarke

Brian Paul Wagner

Christopher F Kirby

Jeffrey David Hartman

Ragini Saxena

John B Goodell

Matthew S Torpey

Harold Clifton Hearne, Iii

Archer S Mitchell

Michael J Lee

Andrew Christian Loyd

Steven Mark Buchoff

Michel E Aumer

Stephen D Vancampen

Sarat Saluru

John R Mason, Jr

Evan B Jones

Justin A Parke

Harlan C Cramer

One example includes an acoustic resonator filter bank system. The system includes a multiplex passive filter that is configured to provide a plurality of filtered versions of a radio frequency (RF) input signal. The system also includes a filter bank that comprises a plurality of filter blocks that are each configured to provide a plurality of pass-bands across a frequency spectrum. Each of the filter blocks includes an acoustic resonator. The system further includes a switch matrix that is configured to provide one of the filtered versions of the RF input signal to one of the filter blocks in the filter bank to provide an RF output signal having a frequency band corresponding to a respective one of the pass-bands.

Acoustic resonator filter bank system

A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.

Castellated superjunction transistors

An enhancement-mode (e-mode) field effect transistor (FET) comprises a buffer layer, and a superlattice of conducting channels on the buffer layer and including a trench that cuts down through the superlattice into the buffer layer and separates the superlattice into a source-access region and a drain-access region, wherein the buffer layer forms a bottom of the trench. The e-mode FET includes a source and a drain adjacent to the source-access region and the drain-access region, respectively. The e-mode FET further includes a gate in the trench, such that a voltage above a threshold voltage of the e-mode FET applied to the gate induces a current channel in the buffer layer underneath the gate, which electrically connects the source-access region to the drain-access region to turn on the e-mode FET, and (ii) a voltage below the threshold voltage applied to the gate eliminates the current channel, which electrically disconnects the source-access region from the drain-access region to turn off the e-mode FET.

Enhancement mode saddle gate device

A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.

Integrated enhancement mode and depletion mode device structure and method of making the same

A vertical transistor is provided that includes a base structure and a superlattice structure overlying the base structure. The superlattice structure comprises a multichannel ridge having sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge. The vertical transistor also includes a source region that overlies the base structure and is in contact with a first end of the superlattice structure, a floating drain that overlies the base structure and is in contact with a second end of the superlattice structure, and a drain. When the vertical transistor is in an 'ON' state, current flows from the source region through the channels of the multichannel ridge to the floating drain, which funnels the current to the drain through at least a portion of the base structure.

Vertical superlattice transistors

A circuit is provided that includes a castellated channel device that comprises a heterostructure overlying a substrate structure, a castellated channel device area formed in the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, and a three-sided castellated conductive gate contact that extends across the castellated channel device area. The three-sided gate contact substantially surrounds each ridge channel around their tops and their sides to overlap a channel interface of heterostructure of each of the plurality of ridge channels. The three-sided castellated conductive gate contact extends along at least a portion of a length of each ridge channel.

A transistor device comprises a base structure and a superlattice of conducting channels overlying the base structure. The superlattice of conducting channels includes source and drain access regions spaced-apart from each other, a ledge between and spaced-apart from the source and drain access regions, and source-side alternating multichannel ridges and trenches that extend from the source access region to the ledge, each ridge having a topside and opposing sidewalls that each extend from the ledge to the source access region. The transistor device includes gate metal that covers each ridge continuously from the ledge to the source access region, such that the gate metal completely covers the topside of the ridge and edges of the conducting channels that intersect the sidewalls of the ridge.

Drain ledge for self-aligned gate and independent channel region and drain-side ridges for SLCFET

One embodiment of the invention includes a reconfigurable circuit comprising a phase-change material switch. The phase-change material switch includes an actuation portion configured to receive a control signal having one of a first state and a second state and to emit a first heat profile in response to the first state of the control signal and a second heat profile in response to the second state of the control signal. The phase-change material switch also includes a switch portion comprising a phase-change material in proximity with the actuation portion. The switch portion can be selectable between a conducting state in response to the first heat profile to conduct an input signal from an input to an output of the phase-change material switch and a blocking state in response to the second heat profile to substantially block the input signal from the input to the output.

Phase-change material reconfigurable circuits

A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.

Methods of making multichannel devices with improved performance

One example includes a semiconductor device. The semiconductor device include a carbon nanotube substrate, a self-assembled monolayer, and a gate oxide. The self-assembled monolayer overlies the carbon nanotube substrate and is comprised of molecules each including a tail group, a carbon backbone, and a head group. The gate oxide overlies the self-assembled monolayer, wherein the self-assembled monolayer forms an interface between the carbon nanotube substrate and the gate oxide.

Self-assembled monolayer overlying a carbon nanotube substrate

A transistor device is provided that includes a base structure and a superlattice structure that overlies the base structure. The superlattice structure comprises a multichannel ridge having sides that extend to the base structure. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge. A three-sided gate configuration is provided that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth. The three-sided gate configuration is configured to re-distribute peak electric fields along the three-sided gate configuration to facilitate the increase in breakdown voltage of the transistor device.

Multichannel devices with gate structures to increase breakdown voltage

An integrated circuit is disclosed that includes a single channel device having a first portion of a single shared heterostructure overlying a substrate structure in a single channel device area, and a gate contact that is in contact with the first portion of the single shared heterostructure. The integrated circuit also includes a multichannel device comprising a second portion of the single shared heterostructure overlying the substrate structure in a multichannel device area, a barrier layer overlying the second portion of the single shared heterorstructure, and a superlattice structure overlying the barrier layer, the superlattice structure comprising a plurality of heterostructures. An isolation region in the single shared heterostructure electrical isolates the single channel device from the multichannel device.

Integrated multichannel and single channel device structure and method of making the same

Multichannel devices with improved performance and methods of making the same

Growing community of inventors

Silver Spring, MD, United States of America

Robert Samuel Howell