National Semiconductor Corporation

Robert S Sleeth

Dennis M Monticelli

William M Howard

Thomas M Frederiksen

Michael E Wright

An integrated circuit buffer inverter is created by cascading an emitter follower stage with a common emitter stage. Both stages include constant collector current loads. The emitter follower stage is adaptively biased from a current mirror that is driven from the collector of the emitter follower for the purpose of maximizing bipolar drive to the common emitter stage.

Buffer inverter circuit with adaptive bias

A carrier current receiver employs a comparator driven differentially to square a received data signal. The same drive signal is applied to a sample and hold circuit in which a capacitor is charged to a level that is related to the data signal offset. A voltage-to-current converter responds to the capacitor charge and feeds a current to the input where it acts to correct the offset.

Differential sample and hold coupling circuit

A communication system for providing both analog information pulses and digital information pulses in a single frame of a pulse train, including circuitry for sequentially multiplexing and modulating a first given number 'm' of analog information input channels to provide 'm' analog information pulses in each frame of the pulse train to convey information respectively representative of the analog information in the analog information input channels; and circuitry for modulating a second given number 'n' of binary information input channels to provide a variable number of digital information pulses and for multiplexing the variable number of digital information pulses in each frame of the pulse train sequentially to the analog information pulses, wherein the variable number of digital information pulses is within a range of 2.sup.n pulses to convey information respectively representative of the binary information in the 'n' binary information input channels. A system for producing analog information signals and binary information signals from such a pulse train includes a binary counter for counting the number of information pulses in each frame of the pulse train; 'm' gates coupled to given stages of the counter for producing 'm' analog information signals respectively conveying the analog information conveyed by the 'm' analog information pulses in each frame; and 'n' gates coupled to given stages of the counter for producing 'n' binary information signals containing binary information that is representative of the number of digital information pulses included in the count for each frame. The counter is reset by a sync pulse included in each frame of the pulse train the binary information is read from the counter in response to the sync pulse to produce the binary information signals.

Simultaneous communication of analog and binary information in a single

A circuit useful in replicating the current produced in a photo diode operated as a current source at zero bias. A second scaled area photo diode is used to bias the circuit to maintain the zero bias over a wide range of illumination levels. The circuit operates in the picoampere range and is linear over at least six orders of magnitude.

Photo electric biased photo diode operational amplifier

An improved comparator circuit is employed to respond to the charge on a capacitor which represents the integrated value of an input current. When the charge exceeds the comparator trip point, an output is generated. The output is delayed in time from the onset of the input current by an amount that is almost exactly linearly proportional to the current magnitude. The improvement comprises a circuit that senses the onset of comparator conduction and supplies the current necessary to operate the comparator. At very low input current values a condition can be reached where the current drawn by the comparator input equals or exceeds the applied current. For this condition an ordinary comparator will never trip. The improved circuit prevents this and, since the current added is only to compensate, the timing function is not seriously perturbed.

Extended range current-to-time converter

A differential amplifier has one input connected to a reference potential and a photo diode connected in series with a level shift to the other input. A negative feedback loop is also coupled into other input. This stabilizes the amplifier and, if the level shift is made equal to the reference potential, biases the photo diode to zero, thereby reducing leakage current. A second feedback loop is used to adaptively bias the tail current in the differential amplifier.

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San Jose, CA, United States of America

Robert S Sleeth