Ati Technologies Inc.

Robert S Mace

Eric Demers

Timothy J Van Hook

A graphics processing circuit includes an anti-aliasing and stippling circuit operative to provide a primitive texture coordinate set in response to vertex data, the anti-aliasing and stippling circuit performing anti-aliasing operations, in parallel, with at least one appearance attribute determination operation on the vertex data, a rasterizer, coupled to the anti-aliasing and stippling circuit, operative to generate a pixel texture coordinate set in response to the primitive texture coordinate set, and apply an appearance value to a pixel defined by the pixel texture coordinate set, and a texture circuit, coupled to the rasterizer, operative to retrieve the appearance value from a corresponding one of a plurality of textures in a multi-texture map in response to the pixel texture coordinate set, the multi-texture map including data representing point, line and polygon texture data.

Apparatus for generating anti-aliased and stippled 3d lines, points and surfaces using multi-dimensional procedural texture coordinates

A graphics processing circuit includes a line end generation circuit operative to generate line aligned end cap data in response to primitive data; and a rasterizer, coupled to the line end generation circuit, operative to generate pixel data representing a line to be rendered, the pixel data including the line aligned end cap data. A graphics processing method includes receiving primitive data for a line to be rendered, the primitive data including start endpoint data and stop endpoint data, determining the height and width of the line in screen space, determining line end cap orientation with respect to the line to be rendered, and determining vertices that define the line to be rendered, wherein the vertices define end caps aligned with the line to be rendered.

Apparatus for generating efficient wide-line ends

The invention provides a method of providing commands to a command memory where a graphics processor will have commands available for execution as long as there are commands available. The command memory includes a first indicator to identify the command location most recently accessed by the graphics processor. A second indicator identifies the number of commands locations available to write commands based on the most recently accessed command location. As a result of the invention, the application processor only checks the availability of space to write commands after it has written enough commands to fill the command memory. On the graphics processor side, the command memory is never empty unless the graphics processor executes and consumes instructions faster than the instructions are written. It is also possible to associate a graphics mode with each address range. In this way, mode can be indicated without specifically sending mode information with each command.

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Scotts Valley, CA, United States of America

Robert S Mace